Part 16: Reset Button And User Button - Alinx ZYNQ7000 FPGA User Manual

PL_LED1
PL_LED2
PL_LED3
PL_LED4

Part 16: Reset Button and User Button

The AX7350B FPGA development board has one reset button RESET and
five user buttons. The reset signal is connected to the PS reset pin of the
ZYNQ chip. The user can use this reset button to reset the ZYNQ system. One
of the five user buttons is connected to the IO of the PS, and the other four
buttons are connected to the IO of the PL. . The reset button and the user
button are all active low. The connection between the reset button and the user
button is shown in Figure 16-1.
ZYNQ pin assignment of the button
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ZYNQ FPGA Development Board AX7350B User Manual
IO_L7P_T1_34
IO_L7N_T1_34
O_L2N_T0_34
IO_L2P_T0_34
U1
BANK
500
ZYNQ
BANK
34
Figure 16-1: Buttons Connection Diagram
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F5 PL User LED1
E5 PL User LED2
G5 PL User LED3
G6 PL User LED4
U3
复位芯片
PS_POR_B
(TCM811)
PS KEY
PS_KEY
PL KEY1
PL_KEY1
PL KEY2
PL_KEY2
PL KEY3
PL_KEY3
PL KEY4
PL_KEY4
RESET