Alinx AC7200 Manual page 7

DSP Slices
PCIe Gen2
GTP Transceiver
Speed Grade
Temperature Grade
FPGA power supply system
Artix-7 FPGA power supplies are V
V . V is the FPGA core power supply pin, which needs to be connected
MGTAVTT CCINT
to 1.0V; V is the power supply pin of FPGA block RAM, connect to 1.0V;
CCBRAM
V is FPGA auxiliary power supply pin, connect 1.8V; V
CCAUX
each BANK of FPGA, including BANK0, BANK13~16, BANK34~35. On
AC7200 FPGA core board, BANK34 and BANK35 need to be connected to
DDR3, the voltage connection of BANK is 1.5V, and the voltage of other BANK
is 3.3V. The VCCO of BANK15 and BANK16 is powered by the LDO, and can
be changed by replacing the LDO chip. VMGTAVCC is the supply voltage of
the FPGA internal GTP transceiver, connected to 1.0V; VMGTAVTT is the
termination voltage of the GTP transceiver, connected to 1.2V.
The Artix-7 FPGA system requires that the power-up sequence be
powered by VCCINT, then VCCBRAM, then VCCAUX, and finally VCCO. If
VCCINT and VCCBRAM have the same voltage, they can be powered up at
the same time. The order of power outages is reversed. The power-up
sequence of the GTP transceiver is VCCINT, then VMGTAVCC, then
VMGTAVTT. If VCCINT and VMGTAVCC have the same voltage, they can be
powered up at the same time. The power-off sequence is just the opposite of
the power-on sequence.
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ARTIX-7 SoM FPGA Core Board AC7200 User Manual
XADC
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1
1 XADC, 12bit, 1Mbps AD
4 GTP, 6.6Gb/s max
-2
Industrial
, V , V
CCINT CCBRAM CCAUX
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rachel.zhou@aithtech.com
, V , V and
CCO MGTAVCC
is the voltage of
CCO