Part 8: Jtag Interface - Alinx AC7200 Manual

Part 8: JTAG Interface

The JTAG test socket J1 is reserved on the AC7200 core board for JTAG
download and debugging when the core board is used alone. Figure 8-1 is the
schematic part of the JTAG port, which involves TMS, TDI, TDO, TCK. , GND,
+3.3V these six signals.
The JTAG interface J1 on AC7200 FPGA core board uses a 6-pin 2.54mm
pitch single-row test hole. If you need to use the JTAG connection to debug on
the core board, you need to solder a 6-pin single-row pin header. Figure 8-2
shows the JTAG interface J1 on the AC7200 FPGA core board.
19 / 30
ARTIX-7 SoM FPGA Core Board AC7200 User Manual
Figure 8-1: JTAG Interface Schematic
Figure 8-2 JTAG Interface on Core Board
Amazon Store:
Sales Email:
https://www.amazon.com/alinx
rachel.zhou@aithtech.com