Alinx AC7200 Manual page 24

PIN55 B14_L18_N
PIN57 B14_L18_P
PIN59 GND
PIN61 B13_L17_P
PIN63 B13_L17_N
PIN65 B14_L21_N
PIN67 B14_L21_P
PIN69 GND
PIN71 B14_L22_P
PIN73 B14_L22_N
PIN75 B14_L24_N
PIN77 B14_L24_P
PIN79 B14_IO0
Board to Board Connectors CON3
The 80-pin connector CON3 is used to extend the normal IO of the
BANK15 and BANK16 of the FPGA. In addition, four JTAG signals are also
connected to the carrier board via the CON3 connector. The voltage standards
of BANK15 and BANK16 can be adjusted by an LDO chip. The default installed
LDO is 3.3V. If you want to output other standard levels, you can replace it with
a suitable LDO.
Pin Assignment of Board to Board Connectors CON3
CON3 Signal Name
PIN
PIN1 B15_IO0
PIN3 B16_IO0
PIN5 B15_L4_P
PIN7 B15_L4_N
PIN9 GND
PIN11 B15_L2_P
PIN13 B15_L2_N
PIN15 B15_L12_P
PIN17 B15_L12_N
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ARTIX-7 SoM FPGA Core Board AC7200 User Manual
U18 3.3V
U17 3.3V
- Ground
T16 3.3V
U16 3.3V
P17 3.3V
N17 3.3V
- Ground
P15 3.3V
R16 3.3V
R17 3.3V
P16 3.3V
P20 3.3V
FPGA Level
Pin Standard
Number
J16 3.3V
F15 3.3V
G17 3.3V
G18 3.3V
- Ground
G15 3.3V
G16 3.3V
J19 3.3V
H19 3.3V
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PIN56 B14_L13_N
PIN58 B14_L13_P
PIN60 GND
PIN62 B14_L3_N
PIN64 B14_L3_P
PIN66 B14_L20_N
PIN68 B14_L20_P
PIN70 GND
PIN72 B14_L19_N
PIN74 B14_L19_P
PIN76 B14_L23_P
PIN78 B14_L23_N
PIN80 B14_IO25
CON3 Signal Name
PIN
PIN2 B15_IO25
PIN4 B16_IO25
PIN6 B16_L21_N
PIN8 B16_L21_P
PIN10 GND
PIN12 B16_L23_P
PIN14 B16_L23_N
PIN16 B16_L22_P
PIN18 B16_L22_N
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Y19 3.3V
Y18 3.3V
- Ground
V22 3.3V
U22 3.3V
T18 3.3V
R18 3.3V
- Ground
R14 3.3V
P14 3.3V
N13 3.3V
N14 3.3V
N15 3.3V
FPGA Level
Pin Standard
Number
M17 3.3V
F21 3.3V
A21 3.3V
B21 3.3V
- Ground
E21 3.3V
D21 3.3V
E22 3.3V
D22 3.3V