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(3) Main clock mode register (MCM)
This register sets the CPU clock (high-speed system clock/Ring-OSC clock).
MCM can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Address: FFA1H
After reset: 00H
Symbol
7
MCM
0
MCS
0
1
MCM0
0
1
Note Bit 1 is read-only.
Caution When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the
86
CHAPTER 5 CLOCK GENERATOR
Figure 5-4. Format of Main Clock Mode Register (MCM)
Note
R/W
6
5
0
0
Operates with Ring-OSC clock
Operates with high-speed system clock
Ring-OSC clock
High-speed system clock
divided clock of the Ring-OSC oscillator output (f
hardware (f
= 240 kHz (TYP.)).
X
Operation of the peripheral hardware with the Ring-OSC clock cannot be
guaranteed. Therefore, when the Ring-OSC clock is selected as the clock supplied
to the CPU, do not use peripheral hardware.
hardware before switching the clock supplied to the CPU from the high-speed
system clock to the Ring-OSC clock. Note, however, that the following peripheral
hardware can be used when the CPU operates on the Ring-OSC clock.
• Watchdog timer
• Clock monitor
• 8-bit timer H1 when f
/2
R
• Peripheral hardware with an external clock selected as the clock source
(Except when the external count clock of TM00 is selected (TI000 valid edge))
Preliminary User's Manual U16846EJ1V0UD
4
3
0
0
CPU clock status
Selection of clock supplied to CPU
In addition, stop the peripheral
7
is selected as the count clock
2
<1>
<0>
0
MCS
MCM0
) is supplied to the peripheral
X
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