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Instruction
Mnemonic
Group
Conditional
BT
saddr.bit, $addr16
branch
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
BF
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
BTCLR
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
DBNZ
B, $addr16
C, $addr16
saddr, $addr16
CPU
SEL
RBn
control
NOP
EI
DI
HALT
STOP
Notes 1.
When the internal high-speed RAM area is accessed or for an instruction with no data access
2.
When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written.
CHAPTER 22 INSTRUCTION SET
Clocks
Operands
Bytes
Note 1
3
8
−
4
3
8
−
3
3
10
4
10
−
4
3
8
−
4
3
10
4
10
−
4
3
8
−
4
3
10
2
6
2
6
3
8
2
4
1
2
−
2
−
2
2
6
2
6
Preliminary User's Manual U16846EJ1V0UD
Operation
Note 2
PC ← PC + 3 + jdisp8 if (saddr.bit) = 1
9
PC ← PC + 4 + jdisp8 if sfr.bit = 1
11
−
PC ← PC + 3 + jdisp8 if A.bit = 1
PC ← PC + 3 + jdisp8 if PSW.bit = 1
9
PC ← PC + 3 + jdisp8 if (HL).bit = 1
11 + n
PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
11
PC ← PC + 4 + jdisp8 if sfr.bit = 0
11
−
PC ← PC + 3 + jdisp8 if A.bit = 0
PC ← PC + 4 + jdisp8 if PSW. bit = 0
11
PC ← PC + 3 + jdisp8 if (HL).bit = 0
11 + n
PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
12
then reset (saddr.bit)
PC ← PC + 4 + jdisp8 if sfr.bit = 1
12
then reset sfr.bit
−
PC ← PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
PC ← PC + 4 + jdisp8 if PSW.bit = 1
12
then reset PSW.bit
12 + n + m PC ← PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
−
B ← B − 1, then
PC ← PC + 2 + jdisp8 if B ≠ 0
−
C ← C −1, then
PC ← PC + 2 + jdisp8 if C ≠ 0
(saddr) ← (saddr) − 1, then
10
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
−
RBS1, 0 ← n
−
No Operation
IE ← 1 (Enable Interrupt)
6
IE ← 0 (Disable Interrupt)
6
−
Set HALT Mode
−
Set STOP Mode
) selected by the processor clock
CPU
Flag
Z AC CY
×
×
×
367
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