NEC 78K0/KB1+ Preliminary User's Manual page 363

Instruction
Mnemonic
Group
8-bit OR A, #byte
operation
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
XOR A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
CMP A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except "r = A"
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
CHAPTER 22 INSTRUCTION SET
Clocks
Operands Bytes
Note 1
2 4
3 6
Note 3
2 4
2 4
2 4
3 8
1 4
2 8
2 8
2 8
2 4
3 6
Note 3
2 4
2 4
2 4
3 8
1 4
2 8
2 8
2 8
2 4
3 6
Note 3
2 4
2 4
2 4
3 8
1 4
2 8
2 8
2 8
Preliminary User's Manual U16846EJ1V0UD
Operation
Note 2
− A ← A ∨ byte
(saddr) ← (saddr) ∨ byte
8
− A ← A ∨ r
r ← r ∨ A
−
A ← A ∨ (saddr)
5
A ← A ∨ (addr16)
9 + n
A ← A ∨ (HL)
5 + n
A ← A ∨ (HL + byte)
9 + n
A ← A ∨ (HL + B)
9 + n
A ← A ∨ (HL + C)
9 + n
− A ← A ∨ byte
(saddr) ← (saddr) ∨ byte
8
− A ← A ∨ r
− r ← r ∨ A
A ← A ∨ (saddr)
5
A ← A ∨ (addr16)
9 + n
A ← A ∨ (HL)
5 + n
A ← A ∨ (HL + byte)
9 + n
A ← A ∨ (HL + B)
9 + n
A ← A ∨ (HL + C)
9 + n
A − byte
−
(saddr) − byte
8
− A − r
− r − A
A − (saddr)
5
A − (addr16)
9 + n
A − (HL)
5 + n
A − (HL + byte)
9 + n
A − (HL + B)
9 + n
A − (HL + C)
9 + n
) selected by the processor clock
CPU
Flag
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
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