The Timetag; The Pseudo-Variable Trcbus - Intel l2ICE User Manual

When the iAPX microprocessor reads the word at 25A, the data bus looks like the following:
D15
The lower byte on the data bus < D 7-D 0> enters the instruction queue before the upper byte
< D 1 5 -D 8 > . The following example illustrates the queue:
From address
258
259
25A
25 B
The word 8BC1 represents the instruction MOV AX,CX, the first instruction of statement
:cmaker#13. The byte 99 represents the instruction CWD, the second instruction of statement
:cmaker#13.
The trace buffer normally collects both execution cycles and bus cycles. It overflows after
1023 frames have been collected. When the trace buffer overflows, it shifts all the frames
toward frame 0. The old frame 0 is lost. The 1023rd frame is always the latest frame.

The Timetag

In the CYLES mode display, the column labeled TIME shows the execution time. Frame 0
always begins at time 0.
The PICE system contains a free-running counter that returns to zero after 2K (2048) counts.
The time increment for each count is set by the TIMEBASE pseudo-variable. Its default is 200
nanoseconds. The largest value you can set TIMEBASE to is 6 milliseconds. TIMEBASE must
be a multiple of 100 nanoseconds.
When the PICE system begins tracing, the value of this free-running counter goes directly into
the trace buffer. The PICE system, however, offsets the value so that frame 0 always begins at
time 0.
If you interrupt the trace, the PICE system starts another clock that runs until tracing resumes.
If a wrap-around occurs (i.e., the counter reaches 2048), the PICE system sets the level flag.
When you resume tracing, the LEVEL column is incremented by one (regardless of how many
wrap-arounds occurred), and the TIME column is reset to 0.0. You will have lost time calibra­
tion because you do not know how many wrap-arounds occurred while the trace was inter­
rupted. Note that these difficulties caused by wrap-around can be avoided by setting
TIMEBASE to a higher value.

The Pseudo-Variable TRCBUS

If you are not interested in bus activity and you want to collect more execution cycles before
overflowing, set the PICE pseudo-variable TRCBUS to FALSE. Its default is TRUE.
3-42
D81D7
99 C1
Data bus
<D 7-D 0>
< D15-D8>
< D7-D0>
< D15-D8>
DO
Queue
(top) 00
8B MOV AX,CX
C1
(bottom) 99 CWD
Introduction to Using the PICE™ System