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Intel l2ICE User Manual

Intel l2ICE User Manual

Integrated instrumentation and in-circuit emulation system
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i n t e T
2
THE l
ICE™
INTEGRATED INSTRUMENTATION
AND IN-CIRCUIT EMULATION
SYSTEM USER'S GUIDE
Copyright 1985, Intel Corporation, All Rights Reserved
Intel Corp., 3065 Bowers Ave., Santa Clara, CA 95051
Order Number: 166298-001

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  • Page 1 T THE l ICE™ INTEGRATED INSTRUMENTATION AND IN-CIRCUIT EMULATION SYSTEM USER’S GUIDE Copyright 1985, Intel Corporation, All Rights Reserved Intel Corp., 3065 Bowers Ave., Santa Clara, CA 95051 Order Number: 166298-001...
  • Page 3 THENCE™ INTEGRATED INSTRUMENTATION AND IN-CIRCUIT EMULATION SYSTEM USER’S GUIDE Order Number: 166298-001 Copyright 1985, Intel Corporation, All Rights Reserved Intel Corporation, 3065 Bowers Avenue, Santa Clara, California 95051...
  • Page 4 Intel's software license, or as defined in ASPR 7 -104.9(a)(9). No part of this document may be copied or reproduced in any form or by any means without prior written consent of Intel Corporation. Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein.

  • Page 5: Table Of Contents

    The Emulation Base Module......................1-10 System Interface C a b le s........................1-11 High-Speed M em ory......................... 1-11 Optional High-Speed Memory Board....................1-11 The Intel Logic Timing Analyzer (iLTA)..................1-11 Emulation Personality M odules....................... 1-11 Software O verview ..........................1-12 Software Environment........................1-12 The PICE™...
  • Page 6 CHAPTER 2 GUIDE TO THE PICE™ SYSTEM TUTORIAL_______________ Page Tutorial U se ............................2-1 Invoking the Tutorial During Program Debugging ............... 2-2 Deactivating the Tutorial........................2-2 Reactivating the Tutorial........................2-2 Tutorial Screens and S tructure......................2-2 Copies of Selected Tutorial S creens....................
  • Page 7 Page Program Variables and Symbolic Debugging.................. 3-16 Program Variables and the PICE™ Memory Types............... 3-18 Managing the Memory and I/O S p a c e s....................3-18 The PICE™ Memory M a p ....................... 3-19 Mapping Input/Output........................3-21 Simulating I/O from the C onsole....................3-22 Simulating I/O with a Debug P ro c ed u re..................
  • Page 8 Page Non-Maskable Interrupt Line and Interrupt Line............... 4-4 Non-Maskable Interrupts and Program Stepping............... 4-4 Synchronization between the Prototype and the P ro b e ............. 4-4 User-Accessible Test P o in ts......................4-4 Coprocessor Considerations......................4-6 Inability to Break when RESET Is A sserted ................4-6 Getting a User NMI while in Emulation Mode ..............
  • Page 9 Page Using the Initialization Segment....................4-25 Reading from and Mapping to Mapped Memory or I /O ............4-26 Pascal-286 and FORTRAN-286 Array Size................4-26 CHAPTER 5 COPROCESSOR SUPPORT____________________________ Mapping Restrictions When Using Coprocessors................5-1 The PHANG Pseudo-Variable......................5-1 The 8087/80287 Numeric Data Processors..................5-1 The COENAB Pseudo-Variable......................
  • Page 10 2 80186/80188 Segment Boundary Increments................4-10 1 Coprocessor Pseudo-Variable Interaction................. 5-2 8086/8088 Emulation Personality Module Jumper Configurations........A-6 Jumpering for 8087 Support...................... A-7 Intel Host Installation A ppendixes................... A-21 The A Configuration Command Values................... B-3 The AF Configuration Command Values................. B-4 FIGURES_____________ ;...
  • Page 11 FIGURES (continued)______________________________________________ Page Sample Trace Buffer Displays in Both Modes for Emulation with the System Register EV EN W ORD ........................3-50 Sample Trace Buffer Displays in Both Modes for Emulation Using the Event Register ODDWORD........................... 3-52 Sample Trace Buffer Displays in Both Modes for Emulation with the System Register EV EN BYTE.........................

  • Page 13: Preface

    PREFACE ■ ■ ■ ■ ■ in te rs This manual introduces Intel’s Integrated Instrumentation and In-Circuit Emulation (PICE™) system. It assumes that you are familiar with the architecture of the iAPX 86, iAPX 88, iAPX 186, iAPX 188, and iAPX 286 microprocessors. It also assumes that you are familiar with the concept of in-circuit emulation.
  • Page 14 This publication provides an overview of the PICE system. It describes the hardware and software, provides some general application information, and lists the system specifica­ tions. The data sheet is available through Intel sales offices as well as the Intel Literature Department.
  • Page 15 Hardware Reference Publications • Memory Components Handbook, order number 210830. This catalog contains data sheets on the memory components manufactured by Intel Corporation. • Microsystems Components Handbook, order number 230843 (two volumes). These handbooks contain data sheets on the microprocessor and peripheral products man­...
  • Page 16 • iAPX286 Operating Systems Writer’ s Guide, order number 121960. This book is written for systems designers, operating system designers, and programmers using the Intel iAPX 286 microprocessor in its protected, virtual-address mode. • PL/M-86 Programming Manual, order number 980466.
  • Page 17 elements Items for which you must substitute a value, expression, file name, etc., are in lowercase letters and italicized. {menu} Braces indicate that you must select one and only one of the items in the enclosed menu. {menu}* Braces followed by an asterisk (*) indicate that you must select at least one of the items in the enclosed menu [menu] Brackets indicate optional items of which you can select one and only one.

  • Page 19: Revision H Isto Ry

    REVISION HISTORY DATE REV. Original Issue. 9/85 -001 xvii/xviii...

  • Page 21: Service Information

    4. The shipping and billing address. 5. If the Intel Product warranty has expired, a purchase order number is needed for billing purposes. 6. Be sure to advise the Center personnel of any extended warranty agreements that apply.
  • Page 22 Air Cap SD-240, manufactured by the Sealed Air Corporation, Hawthorne, N.J. Securely enclose it in a heavy-duty corrugated shipping carton, mark it “ FRAGILE” to ensure careful handling, and ship it to the address specified by the Intel Product Service Center.

  • Page 23: The Microcomputer Development Process

    PICE™ SYSTEM OVERVIEW in y B B i Intel’s Integrated Instrumentation and In-Circuit Emulation (PICE™) system offers real-time hardware and software emulation for designs using the iAPX 86, iAPX 88, iAPX 186, iAPX 188, and iAPX 286 microprocessor systems. This chapter is an overview of the PICE system and its operating environment. It contains the following sections.

  • Page 24: Generalized Hardware Design Steps

    PARTS OF THE DEVELOPMENT PROCESS AIDED BY THE MICROCOMPUTER DEVELOPMENT SYSTEM AND IN-CIRCUIT EMULATOR I - ----------------------------------------------------------------- Figure 1-1 Typical Microcomputer Development Process Generalized Hardware Design Steps Although the complexity of hardware design varies from one design to another, the general process is the same.

  • Page 25: Hardware/Software Integration

    An Introduction to the l ICE™ System Intel developed the PICE system to address the requirements of designers who use Intel’s iAPX microprocessors. The PICE system is a second-generation design tool that provides the follow­ ing advantages: •...

  • Page 26: The Base Configuration Of The Pice™ System

    CPU chip and jumpers on the buffer and personality boards. NOTE Probe CPU chips must be provided by Intel. All probes use either bond-out chips or specially tested microprocessors. • Symbolic debugging support for programs written in assembly language, PL/M, C, Pascal, and FORTRAN by both PSCOPE-86 and the PICE system command language.

  • Page 27: A Basic Pice™ System

    1160-A Figure 1-2 A Basic PICE™ System rest of the on-board RAM contains PICE system software that implements probe-specific commands. • The break/trace board, which contains two programmable event machines that implement the break and trace specifications. • The emulation clips assembly, which enables the PICE system to assert signals to the prototype hardware and to read signals from the prototype hardware.

  • Page 28: Pice™ System O P Tio N S

    The base configuration of the PICE system contains the following software. • The PICE system host software, which implements the non-probe-specific PICE system commands. After the PICE system software is loaded, it resides in the host development system. • The PICE system probe (personality module) software, which implements the probe- specific PICE system commands.

  • Page 29: Pice™ System Accessories

    Figure 1-3 A Maximum Configuration PICE™ System PICE™ System Accessories The PICE system accessories are as follows. • An emulation clips assembly that consists of an emulation clips pod, an emulation clips cable, and an emulation clips terminator. • Two logic probe pods (channels 0-7 and 8-F) that supplement the iLTA pods. Each pod can be ordered separately.

  • Page 30: Hardware Overview

    Each PICE system requires one host interface board. It resides in the host development system and controls up to four instrumentation chassis. For Intel hosts, the host interface board is a MULTIBUS® master board that makes possible direct memory access (DMA) to MULTIBUS board memory by the PICE system;...

  • Page 31: Pice™ System Hardware Components

    Table 1-1 PICE™ System Hardware Components Instrumentation chassis Host interface board Emulation base module Break/trace board Map-I/O board Buffer base assembly Emulation buffer board Probe buffer box base Probe buffer box cable Emulation clips assembly Emulation clips pod Emulation clips cable Emulation clips terminator Emulation clips microhooks System cables...

  • Page 32: The Emulation Base Module

    The Emulation Base Module The emulation base module provides a generic environment that an emulation personality module tailors to the microprocessor being emulated. Each instrumentation chassis contains one emulation base module. A fully-expanded MCE system contains four instrumentation chassis and four emulation base modules, each with an emulation personality module. The emulation base module consists of the following hardware: •...

  • Page 33: System Interface Cables

    Each PICE system can contain two OHS memory boards for a total of 256K bytes of OHS memory. The Intel Logic Timing Analyzer (iLTA) The iLTA is a test and measurement module which combines all the features of a stand-alone logic analyzer with the event machines and storage capabilities of the PICE system.

  • Page 34: Software Overview

    In addition to supporting real-time emulation and debugging for the specified microprocessor, the emulation personality modules also provide debugging support for coprocessors. For ex­ ample, the PICE system 8086/8088 and 80186/80188 emulation personality modules provide debugging support for the 8087 coprocessor. The 80286 emulation personality module pro­ vides debugging support for the 80287 numeric processor extension.

  • Page 35: The Pice™ System Debugging Capabilities

    PSCOPE 86 PICE™ SYSTEM SOFTWARE DEBUGGING PICE™ SYSTEM____________ [8 0 8 6 /8 0 8 8 EMULATION | 801 8 6 /8 0 1 8 8 EMULATION 8 0 2 8 6 EMULATION IjLTA HARDWARE DEBUGGING 1 2 0 0 A Figure 1-4 The PICE™...

  • Page 36: The Pice™ System Command Language

    • Intellec Series IV development system For the iNDX operating system, the work device must be defined. For example, assume that you specify a hard disk named WDO for the work device and the directory WORKDIR to contain the work file. The command is LNAME DEFINE :W0RK: FOR /WDO/WORKDIR •...

  • Page 37: The Pice™ System Software

    The PICE system pseudo-variables are system-defined variables that can be used in expres­ sions but cannot be removed by the user. For example, the dollar sign ($) pseudo-variable represents the current execution point. The PCHECK pseudo-variable is a probe-specific Boolean pseudo-variable. Setting PCHECK to TRUE enables protection checking for the 80286 probe.

  • Page 38: The Ilta Disks

    The PSCOPE-86 Disk The PSCOPE-86 disk is included with every FICE system hosted by an Intel host. PSCOPE-86 software is an option for IBM PC hosts. The contents of the PSCOPE.86 disk for Intel hosts are as follows: •...

  • Page 39: Pice™ System Specifications

    • M files. Each module in the tutorial is activated by the commands in its associated M file. For example, to activate module B, the commands in file M.B are executed. • I2ICE.MAC file. This I2ICE.MAC file is specially designed for use with the tutorial. When PICE software is activated, after the host and probe software is loaded, the I2ICE- .MAC file is executed.

  • Page 40: System Performance

    NOTE References to the Model 800 assume that it has been upgraded to a Series III. The Intellec Series III must have the following configuration: • An integral system console • Two double-density disk drives • The iSBC 012B memory board •...

  • Page 41: Emulation Clips

    Emulation Clips The emulation clipsin lines are sampled once every bus cycle when the address bits become valid on the address bus. During emulation, the PICE system records the value of these lines in the trace buffer, once every execution cycle. Because not all clips data is stored, a clips value can cause a break, and its data will not appear in the trace buffer.

  • Page 43: Chapter 2 Guide To The Pice™ System Tutorial

    PICE tutorial. The tutorial is the quickest way to become acquainted with the wide variety of PICE commands. Intel recommends that new users complete the main path of the tutorial (and many of the tutorial aid modules) before they proceed to debug their own programs.

  • Page 44: Invoking The Tutorial During Program Debugging

    Invoking the Tutorial During Program Debugging If you invoke the PICE software without invoking the tutorial, and later you wish to review information in one or more of the tutorial screens, you can invoke the tutorial by entering the following command. INCLUDE pathname I2ICE.MAC NOUST The pathname provides the location of the PICE software.
  • Page 45 I H I C E T u t o r i a l (Versionx-y SCRl: WELCOME TO I2ICE Copyright nfi5-. Intel Corporation M = Go to main menu Welcome to the I2ICE system. This tutorial will N = Next screen...

  • Page 46: Copies Of Selected Tutorial Screens

    NOTE 1. For Intel hosts, commands are entered with the < RETURN > key. For IBM PC hosts, use the < Enter > key. 2. On Series III hosts, pressing < C T R L > and D at the same time produces an asterisk prompt (*), but this prompt is not for PICE software;...

  • Page 47: An Overview Of The Tutorial Structure

    SCR2 : MAINMENU The main purpose of this tutorial is to help you M = Go to main menu learn the I2ICE command language and to show you N = Next screen how to conduct an emulation session - There are P = Previous screen three groups of tutorial screens: main path screens <...

  • Page 48: List Of All Tutorial Screens

    AI D1 : EMULATION AID MODULES MENU AIDl: EMULATION AID MENU Listed below are the modules that contain Go to main menu additionalinformationonlEICEemulation Next screen topics - Typing the module name sets the Previous screen prerequisites for starting the module and (Suit tutorial displays the first screen in that module.
  • Page 49 Using Multiple IEICE Probes MOD_Y <RETURN> PSCOPE-flb: An Overview H0 D_Z <RETURN> Intel Logic Timing Analyzer (iLTA) Select a menu item • NOTE: The tutorial for IBM hosts does not have MOD_Z. Figure 2-4 Menu for the PICE™ Feature Modules: AID2 •...
  • Page 50 SCREEN OUTPUT TRANSLATION UNIT D PORT OODEH OUTPUT BYTE OQOAH fUNIT 0 PORT OOOEH OUTPUT BYTE DOODH fUNIT 0 PORT OODEH OUTPUT BYTE 0050H line feed f UNIT D PORT OQOEH OUTPUT BYTE OOblH carriage return f UNIT □ PORT ODDEH OUTPUT BYTE OObHH fUNIT 0 PORT OODEH OUTPUT BYTE 00L4H fUNIT...

  • Page 51: Tutorial Structure

    MAIN TUTORIAL PAT " MOD...B SCRB1 • • »SCRB2 MOD_C SCRC1 M O D ^ Z SCRZ1 •••S C R Z 4 NOTE: EACH MODULE CAN BE ENTERED W ITHO UT COMPLETING PREVIOUS MODULES. TO LOAD A L L PREREQUISITES, TYPE MOD H OR MOD LETTER INSTEAD OF SCR #...
  • Page 52 Table 2-1 Main Tutorial Path Screens Screen Screen Module Topic Name Title Name SCR1 Welcome to I2ICE (These screens are reproduced in Figures 2-1 through 2-4.) SCR2 Main Menu AID1 Emulation Aid Menu AID2 Aid Features Menu Introduction In this module, you work with MODI SCR3 SCR4...
  • Page 53 Table 2-2 Emulation Aid Module (AID1) Screens Screen Screen Module Name Title Topic Name SCRA1 HELP Screens (Reference SCR7) MOD_A SCRB1 Syntax MENU 1 (Reference SCR8) MOD_B SCRB2 Syntax MENU 2 SCRC1 Line Editor (Reference SCR10) MOD_C SCRD1 History Buffer (Reference SCR18) MOD_D SCRE1...
  • Page 54 PSCO PE-86 MOD„Z SCRZ1 iLTA Intro Module Z introduces the SCRZ2 Install iLTA Intel Logic Timing Analyzer. Intel L o g ic SCRZ3 Trigger Setup Tim ing SCRZ4 Timing Display A n a ly z e r— SCRZ5 State Display iLTA Guide to the PICE™...

  • Page 55: Tutorial Index

    Tutorial Index The following index correlates PICE tutorial screen suffixes with tutorial topics and PICE commands. To display any screen cited in the index, add the tutorial screen prefix SCR to the suffix and type < RETURN> (or < Enter > ). For example, if the index entry of interest is K l, type SCRK1 <...
  • Page 56 Subject Screen Suffix Error info K l, K2, K3 ESC key Event specifications FLAGS W2 ■ Fully qualified reference 1 7 ,2 6 ,4 0 ,4 3 GO FROM 14, 15, 16, 21, 25, 33,42, H6 GO TIL 35, 37,42 GO/TRACE GO USING HELP...
  • Page 57 Subject Screen Suffix Patch, assembly-language 33, J 1 through J5 Patch, high-level 30,31 PINS POINTER PORTDATA H4 through H8 PRINT W1 through W6 Probes Probe status PROCs 20, 30, 31,32, E l through E4 VI through V5 Prototype hardware Y l, Y2, Y3 PSCOPE-86 Pseudo-variables PSTEP...

  • Page 58: Tutorial Program Listings

    Screen Suffix Subject Variable address 1 7 ,2 3,24 Variable values 22, 23, 33, X7 WAIT E2, M4, N3 WRITE Tutorial Program Listings The PICE tutorial disk has source programs in PL/M, C, FORTRAN, and Pascal. However, the tutorial is designed to only be used with the PL/M program. The C, FORTRAN, and Pascal programs are included on the tutorial disk for convenience.

  • Page 59: M Program Listing For The Two-Bug Version Of The Change Maker Program

    There are two versions of the PL/M program in source code—the code in each version is the same but the comments are different. These two versions are used in the tutorial for two tutorial sessions that introduce the PICE screen editor. In the sessions, users are asked to edit the PL/M source code to correct the two bugs detected during emulation.
  • Page 60 /* time; also writes an input byte to char BYTE; /* an output port char = INPUT(in_port); IF char = ODH THEN CALL write (@lf_cr, 1); CALL write (@char, 1); RETURN char; 10 2 END read; /* Write text_cnt characters */ 11 2 write: PROCEDURE (text__ptr, text_cnt);...
  • Page 61 text BASED text_ptr STRUCTURE (cnt BYTE, string(1) BYTE), Pointer location can change with the program text_cnt BYTE; 35 2 IF value = OTHEN RETURN; 36 2 CALL write (@(' '), 2); 37 2 Insert 2 blanks 38 2 CALL write_decimal(value); Value of change text_cnt = text.cnt;...
  • Page 62 63 2 CALL write(@text.string, text.cnt): 64 2 value = 0; 65 2 not_done = TRUE; DO WHILE not_done; Flag 66 2 67 3 char = read; IF (char > = '0 ') AND (char < = '9 ') THEN Keyboard entry can 68 3 be 0 through 9 69 3...

  • Page 63: The Asm-86 Listing For The No-Bug Version Of The Change Maker Program

    The ASM-86 Listing for the No-Bug Version of the Change Maker Program The ASM-86 language listing for the change maker program was obtained by compiling the corrected version of the PL/M program using the CODE option. It is recommended that the compilation be done using OPTIMIZE(O) when debugging.
  • Page 64 ASSEMBLY LISTING OF OBJECT CODE (continued) PUSH 0109 010A 8BEC BRSP ; STATEMENT# 13 C70612000000 I,OH 01OC 8 B4604 AX,[BP].TEXT__CNT 0112 0115 3B061200 0116 AX,I 011A 7303 $ + 5H 011C E91A00 ; STATEMENT # 14 011F C45E06 BX,[BP].TEXT_PTR 0122 8B361200 SI,I 0126...
  • Page 65 ASSEMBLY LISTING OF OBJECT CODE (continued) 0163 DIGIT_STACK[BX],DL 0164 88971F00 ; STATEMENT # 22 8B4604 AX,[BP].VALUE 0168 B90A00 CX,0AH 016B 31D2 DX,DX 016E F7F1 0170 894604 [BP].VALUE,AX 0172 ; STATEMENT # 23 0175 E9CEFF ; STATEMENT # 24 0178 AX,STK_XOP 8B061600 017C 89061400...
  • Page 66 ASSEMBLY LISTING OF OBJECT CODE (continued) WRITE E848FF 01 BE CALL ; STATEMENT # 32 01C1 01C2 C20200 CONVERT_DECIMAI__DIGIT ENDP ; STATEMENT #33 PRINT_COIN PROC NEAR PUSH 01C5 BP,SP 01C6 8BEC ; STATEMENT # 35 [BP].VALUE,OH 01C8 837E0400 $ + 5H 01CC 7403 01CE...
  • Page 67 ASSEMBLY LISTING OF OBJECT CODE (continued) PUSH 0213 CALL WRITE 0214 E8F2FE ; STATEMENT # 43 0217 B80000 AX,OFFSET(LF_CR) PUSH 021A PUSH 021B B80200 AX,2H 021C 021F PUSH 0220 E8E6FE CALL WRITE ; STATEMENT # 44 0223 0224 C20600 PRINT_COIN ENDP ;...
  • Page 68 ASSEMBLY LISTING OF OBJECT CODE (continued) PUSH 0266 CALL WRITE 0267 E89FFE ; STATEMENT #52 B81300 AX,OFFSET(S_TEXT) 026A PUSH 026D PUSH 026E 026F FF360400 PUSH DOLLARS E84FFF PRINT__COIN 0273 CALL ; STATEMENT #53 0276 B81C00 AX,OFFSET(Q_TEXT) 0279 PUSH 027A PUSH 027B FF360600 PUSH...
  • Page 69 ASSEMBLY LISTING OF OBJECT CODE (continued) @13: ; STATEMENT #60 02C0 02C1 PAYMENT ENDP ; STATEMENT # 61 GET _INPUT PROC NEAR 02C2 PUSH 02C3 8BEC BP,SP ; STATEMENT #63 C45E04 BX,[BP].TEXT_PTR 02C5 02C8 8D4701 AX,TEXT[BX + 1 H] 02CB PUSH 02CC PUSH...
  • Page 70 ASSEMBLY LISTING OF OBJECT CODE (continued) ; STATEMENT # 70 8B061C00 AX,VALUE 0313 0317 B90A00 CX,0AH 031A F7E1 VALUE,AX 031C 89061 COO ; STATEMENT # 71 8A062600 AL,CHAR 0320 0324 B400 AH,OH 0326 03061 COO AX,VALUE 81E83000 AX,30H 032A VALUE,AX 032E 89061 COO 0332...
  • Page 71 ASSEMBLY LISTING OF OBJECT CODE (continued) CALL 0020 E89F02 GETJN PUT PURCHASED,AX 0023 89061000 ; STATEMENT #82 0027 B80000 AX,OFFSET(LF_CR) PUSH 002A PUSH 002B AX,2H 002C B80200 002F PUSH E8D600 CALL 0030 WRITE ; STATEMENT # 83 0033 8B060E00 AX,PAID 0037 2B061000 AX,PURCHASED...

  • Page 72: Sample Programs In C, Fortran, And Pascal

    ASSEMBLY LISTING OF OBJECT CODE (continued) 31D2 DX,DX 0091 0093 F7F1 COINS,DX 0095 89160000 ; STATEMENT # 90 AX,COINS 0099 8B060000 009D CX,5H B90500 31D2 DX,DX 00A0 00A2 F7F1 00A4 89060800 NICKELS,AX ; STATEMENT #91 AX,COINS 00A8 8B060000 CX,5H 00AC B90500 00AF 31D2...

  • Page 73: A Change Maker Program In C

    Before emulating these programs with the system, they must be compiled, linked, located, and memory mapped in the PICE system. You will also have to add I/O routines if you want to simulate user interaction. A Change Maker Program in C To debug a C program using the PICE system, use C86 V2.0 or higher.

  • Page 74: A Change Maker Program In Fortran

    dimes = remainder /1 0 ; remainder = remainder °/o 10; nickels = rem a in d e r/5; remainder = remainder pennies = remainder; } /* END * / A Change Maker Program in FORTRAN The Changemaker Program This program assumes an amount paid for an item of an assumed value and computes the change due and how to make that change in U.S.

  • Page 75: A Change Maker Program In Pascal

    A Change Maker Program in Pascal PROGRAM cmaker (INPUT, OUTPUT); This Pascal program is non-interactive. It contains a purchase price and an amount paid, and puts the change in the memory location of the variables. purchase INTEGER paid INTEGER change INTEGER coins INTEGER...
  • Page 76 PROCEDURE payout; ( * how many dollars, quarters, etc. *) BEGIN dollars change DIV coins change MOD quarters coins coins coins dimes coins coins coins nickels coins pennies coins END; BEGIN (* mainline *) in it (* clear memory *); getinput (* user interaction *);...

  • Page 77: Invoking Pice™ S Oftw Are

    INTRODUCTION TO USING THE l ICE™ SYSTEM In the installation appendix for your host software, you are encouraged to install the PICE tutorial software so that you can quickly learn PICE commands and features. The information in this chapter provides more detail on many of the topics covered in the tutorial. The main sections of the chapter are the following: •...
  • Page 78 If your system disk does not contain a file called I2ICE.CRT, the PICE system assumes an Intel or IBM PC terminal. If your system disk contains a macro file called I2ICE.MAC, the PICE system executes the PICE commands in that file upon invocation.

  • Page 79: Entering Pice™ System Com Mands

    If you rename any of the PICE files and you want them to be used as the default files during invocation, you must rename them all. For example, if you want MYFILE for a name, you must change I2ICE.CRT to MYFILE.CRT, I2ICE.MAC to MYFILE.MAC, I2ICE.OVE to MYFILE.OVE, I2ICE.OVH to MYFILE.OVH, and the probe file I2ICE.086 (for the 86/88 probe) to MYFILE.086.

  • Page 80: Multiple Commands On A Line

    Multiple Commands On a Line To enter more than one command on a line, separate each command with a semicolon (;). The following example shows two commands on the same line. * m ? 0 LENGTH 32K HSjMAPIO 0 LENGTH S4T ICE Comments Enclose a comment within a slash-asterisk combination.

  • Page 81: The Pice™ Command History Buffer

    When you invoke the PICE software, the first line of the menu appears on the bottom of the screen. Call up subsequent lines by pressing the TAB key. The menu is circular in one direc­ tion. Press TAB enough times, and you come back to where you started. You cannot reverse the menu.

  • Page 82: String Handling

    use the line-editing functions to modify the command. Entering a carriage return (or, for IBM PC hosts, using the < Enter> key) executes that command. The new version becomes the latest entry in the command buffer. The old version is still in its original place in the buffer. String Handling A string has memory type CHAR.

  • Page 83: Block Commands

    The INSTR function searches a string for a substring and returns the index on which the substring begins. As shown in the following example, the index is always in decimal. * INSTRf' abedefghijklmti V klro') For more information on string commands, see the string command entries in the PICE™ System Reference Manual.

  • Page 84: Creating Debug Objects

    Creating Debug Objects Debug objects are uniquely-named, user-created software constructs that the PICE system uses to manage the debugging environment. The four types of debug objects are debug procedures, LITERALLY definitions, debug registers, and debug variables. Debug procedures are user-named groups of PICE commands. Execute them just as you would an PICE command.

  • Page 85: Creating A Literally Definition

    Creating a LITERALLY Definition The following example uses the DEFINE command to create a LITERALLY definition. *0EFJNE LITERALLYdef - DEFINE' Now def can be used in place of DEFINE. The character string to the right of the equal sign can be up to 254 characters long. You can also use a LITERALLY definition to replace a command line as shown in the follow­...

  • Page 86: The Pice™ Screen Editor

    An mtype is one of the PICE memory types. (See the memory types section in this chapter for more information on memory types and on creating debug variables.) If you do not set the debug variable equal to a value, the PICE system assumes zero. The PICE™...

  • Page 87: Deleting And Moving Text

    What you enter is inserted into the buffer at the cursor position. Return to the main menu by pressing the ESC key or by entering CTRL-C. (Note that CTRL-C deletes all the text you inserted.) Deleting and Moving Text The PICE screen editor uses the same control characters as the line editor. To delete a character or line, use the CTRL-A, CTRL-F, CTRL-X, or CTRL-Z key.

  • Page 88: Exiting The Screen Editor

    Exiting the Screen Editor To exit the screen editor, return to the main menu and press the Q key. If you were editing a debug procedure, the bottom line displays the following quit menu: A b o r t E x e c u t e I n i t W r i t e If you were editing an external file, the bottom line displays the following quit menu:...

  • Page 89: Include Files: The Include, Put, And Append Commands

    activity is written to that file. You can stop recording in the list file by entering the NOLIST command. You can restart listing, but if you use the same pathname, you are prompted as follows: Overwrite existing file? (y or [n]). If you do not want to overwrite the existing list file, answer “...

  • Page 90: The Load And Save Commands

    After you enter the INCLUDE command, the PICE system displays the contents of the speci­ fied include file on the console screen. You can suppress that display with the NOLIST option, as in the following standalone Series III example: INCLUDE :F1:<Jeb.00t NGUST The LOAD and SAVE Commands Program files must contain absolute code.

  • Page 91: Memory Types

    Memory Types A debug variable always has one of the following PICE memory types associated with it, ADDRESS 16-bit unsigned number Assembly language mnemonic, read-only 80-bit packed binary coded decimal number BOOLEAN 8 bits, but only the least significant bit (LSB) has meaning (TRUE has LSB = 1;...

  • Page 92: Debug Variables

    Debug Variables A debug variable is defined with an PICE command during a debugging session. With certain restrictions, you can assign debug variables of one type equal to debug variables of another type as shown in the following example: * DEFINE WORD answer * DEFINE BYTE ans * 4FH * answer * ans...
  • Page 93 □ D E O :OOOCH BCAOOl HOV SP-.Q1AQH n+mt,T O D E D : OODFH EEflElEDEDD (10V D S , CS : WORD PTR ODDEH /*ISTEP*, O D E O :DOIMH EA0AD0E10D JMP (#1)D D E 1 H :OODAH D O E D :D011H : CMAKER#1 □...

  • Page 94: Program Variables And The Pice™ Memory Types

    identifies the symbol, such a reference is always valid. A partially-qualified reference omits the module name and one or more of the outer procedure names. A partially-qualified refer­ ence is valid only if the current execution point is inside the outer-most procedure referenced. Program Variables and the PICE™...

  • Page 95: The Pice™ Memory M A P

    The l2ICE™ Memory Map The user program must be absolute code, and every memory reference must have a unique physical address. The PICE memory map determines where this memory space physically resides. You can split up the memory space among the following: USER The prototype hardware contains the memory.
  • Page 96 To change the memory map, specify a memory partition and a physical location for program memory. For example, to map the first 32K bytes of program memory to HS memory, enter the following command: *MAP OK LENGTH 32K HS A partition is a range of addresses. The partition OK LENGTH 32K represents a starting address of 0 and a range of blocks 32K bytes long.

  • Page 97: Mapping Input/Output

    After the command is executed, program memory values are the following: Address Value at that address .start . start +1 .start+ 2 .start+ 3 .start+ 4 .start+ 5 .start+ 6 The algorithmn used by the PICE system reads from program mem­ ory, even though you designated the partition as WRITE with the MAP command.

  • Page 98: Simulating I/O From The Console

    regardless of where memory or I/O is mapped. When memory or I/O is mapped to MB, OHS, or HS memory or ICE I/O, the data is written to both MB, OHS, or HS memory or ICE I/O and the target system. The data is read from both the target system and MB, OHS, or HS memory or ICE I/O.

  • Page 99: Simulating I/O With A Debug Procedure

    Simulating I/O with a Debug Procedure A debug procedure is a named group of PICE commands. To simulate I/O using a debug procedure, map one or more I/O partitions to ICE and follow the keyword ICE with the name of a previously-defined debug procedure, as follows: *MAPIO 0 LENGTH 64T ICE(money) Input When the user program requests input, the PICE system calls the specified debug procedure,...
  • Page 100 O utput When the user program writes an I/O port which belongs to an I/O partition mapped to ICE- (money), the debug procedure money handles the output. The program cmaker.86 writes to port 64. To change the I/O map so that port 64 is mapped to money, enter the following command: * MAPiO 0 LENGTH 128T ICE<money) The debug procedure must write the output value to the console or store the output value in a...

  • Page 101: The Emulation Clips

    . . . *ELSE IF %0 = = 4 THEN ------ *PORTDATA = 65T ------*END .••*iii . . . *ans=PORTDATA . . . * ELSE answer = PORTDATA . . . *END • • *END . *END The Emulation Clips The emulation clips pod has eight input signals and four output signals.

  • Page 102: Emulating A Program

    *cui*sounr ~ q iy c u p s o u t The two clipsout lines that can be set by users with the CLIPSOUT command are zero by default. The other two clipsout lines are the system break and trace lines. An armed PICE system asserts the system break line when it encounters a breakpoint.

  • Page 103: Compiling The Source File

    Call the file cmaker.SRC and write it on the disk mounted on drive 0. The file’s pathname is :FO:cmaker.SRC. Compiling the Source File This example assumes that the Pascal compiler is on disk drive 1 of a Series III development system and that the source file is on disk drive 0.

  • Page 104: Getting Ready To Emulate

    I2ICE entry in the PICE™ System Reference Manual. The host development system’s console responds with the following sign-on message: SERIES III I2ICE Vx-y Copyright nfift-, llfiS INTEL CORPORATION fib Probe Version Vx.y The asterisk (*) is the PICE prompt.
  • Page 105 The FICE software provides a menu at the bottom of the screen that shows all the commands and parameters you can enter at a particular command level. The following menu is the first menu you see after invoking the PICE software: --- m o r e ---- Use CTAB1 to cycle through prompts when "more"...

  • Page 106: Emulating Your Program

    Emulating Your Program First display the PICE pseudo-variable $, which represents the current execution point. □ 020:000LH The address 20:6 is where LOC86 placed the beginning of your program. This address is easier to remember if you give it a name (such as begin) by defining a debug variable, as follows.
  • Page 107 The break occurs. The program has not yet completed execution. It has already set coinrelease (presumably to 1 because this time you have a nickel coming), but it has not yet written coin­ release to the output port. You can display the value stored in coinrelease symbolically. You can also display both the value and address of coinrelease by applying the WORD memory template.
  • Page 108 To save the definitions of the debug objects for future use, write them to a file named deb.001 with the PUT command. (This example assumes that you will be writing to drive :F1:. For information on how to specify directories and drives on the Series IV or on an IBM PC host, see the Pathname entry in the PICE™...

  • Page 109: Breaking, Tracing, And Arming

    Breaking, Tracing, and Arming This section explains how to set breakpoints and how to control and interpret the trace buffer. The Example The sample program used in this section is an expansion of the program used in previous section. This version first reads the amount tendered (paid) and the amount of the purchase (purchase).

  • Page 110: Emulating A User Program

    Emulating a User Program The previous section explained that you begin emulation by using the command GO. By de­ fault, GO starts emulation from the current execution point and with the last specifications that were given with the GO command. GO FOREVER is the default condition.

  • Page 111: The Event Machines

    An arm specification specifies both a breakpoint and an arm window. The arm window deter­ mines when the PICE system can recognize the breakpoint. (For more information on what kinds of arm specification conditions can be selected, see the GO entry in the PICE™ System Reference Manual.) For example, the following command opens the arm window only when the procedure payment is executing.

  • Page 112: Arm R Egisters

    Arm R egisters Arm registers set conditional breakpoints that enable breaking within windows. A break win­ dow is opened when an arm condition is encountered and closed when a disarm condition is encountered. For example, you can define an arm register to open the arm window when your program is executing the procedure payment.

  • Page 113: Trace R Egisters

    Trace R egisters Trace registers specify under what conditions trace information is collected. For example, define a trace register called trace 1 that causes the FICE system to begin collecting trace information when your program begins executing statement #12 and to stop collecting trace information at statement #13.

  • Page 114: Interpreting The Trace Buffer

    Interpreting the Trace Buffer The trace buffer contains trace information and consists of 1023 48-bit frames. Using the PRINT command, you can display the trace buffer as either disassembled instructions (IN­ STRUCTIONS mode) or as execution and bus cycles (CYCLES mode). This section contains an example of a trace display.
  • Page 115 * PRINT INSTRUCTIONS ALL FRAME BYTE MNEMONICS OPERANDS UNIT □ : CMAKER#12 CX-.U0RD PTR 0012H □□0 0 0 2 1 Q03FH M AB0E1200 004 0 0 2 1 :0 0 4 3 H M 2BCA UORD PTR 0 0 0 4 H iC X AT0E0400 00b 0 0 2 1 0045H...
  • Page 116 - ► 0021:003FH 00210 + 003F 0024F * m m r cycles a l i CLIPS 1 F RAME UNIT □ EXEC ADR /BUS ADR DATA STATUS TIME LEVEL 00024F f 000 0.0 nanosecs b 000450 d 004B s OODE DU c f 001 b 000254 d Sica s 00D4 CF c f 002...
  • Page 117 The next frame (f 002) is a fetch from the code segment. The data is 89C8. The C8 belongs to statement #12’s second instruction, SUB CX,AX. The 89 begins statement #12’s third instruc­ tion, MOV WORD PTR 0004H,CX. The next frame (f 003) is a data read. The data is 0050 (80 in decimal). This is the read of the program variable paid.

  • Page 118: The Timetag

    When the iAPX microprocessor reads the word at 25A, the data bus looks like the following: D81D7 The lower byte on the data bus < D 7-D 0> enters the instruction queue before the upper byte < D 1 5 -D 8 > . The following example illustrates the queue: Queue From address Data bus...

  • Page 119: Trace Buffer Information

    Trace Buffer Information For more information on the trace buffer, see the entries PRINT and Trace buffer display in the FICE™ System Reference Manual. Hardware Slipping On a Breakpoint Because emulation is in real time, for the 8086/8088 and 80186/80188 probes you cannot break exactly where you specified.

  • Page 120: Even Addresses, Odd Addresses, And Breaking

    Even Addresses, Odd Addresses, and Breaking The iAPX architecture causes a word written to an even address to appear on the data bus once in the normal order (high byte, low byte). A word written to an odd address appears on the data bus twice in reversed order (low byte, high byte) because of the standard 86 architecture.
  • Page 121 * PRINT in s t r u c t io n s n e w e s t s UNIT 0 FRAME BYTE MNEMONICS OPERANDS 3F5 0DA3FEH 3Fb 0Dfl3FFH 3FA Q0fl4D3H WORD PTR 0FC00H-.AX A300FC 3FA 0DA403H 00FC00H- DU-AB12H 3FC 00A4D4H Figure 3-3 Sample Trace Buffer Display in INSTRUCTIONS Mode for Emulation with the System Register EVEN The next example looks at the last 16 cycles in the trace buffer (see Figure 3-4).
  • Page 122 CYCLES NEWEST * m iH T EXEC ADR BUS ADR DATA STATUS CLIPS FRAME TIME LEVEL UNIT □ f 3EF 402.b microsecs 0063FA b f 3F0 b 00S3FE d ‘ ICHO s 0054 CF c 403.2 microsecs 0063FB b f 3F1 f 3F2 403.6 microsecs 0063FC b...

  • Page 123: Byte Writes To Even And Odd Addresses

    * PRINT INSTRUCTIONS NEWEST $ MNEMONICS OPERANDS UNIT 0 FRAME BYTE 3F3 00A3FDH 3FS QDA3FEH 3Fb 0DA3FFH UORDPTRDFCDIH 3Ffl 006400H A3D1FC D0FCD1H-DU-1EABH ------------------------------------ 8 0 8 6 w rites the 12. 3FB 006403H DDFCDEH-Dlil-igABH ------------------------ ► 8 0 8 6 w rites the AB. * PRINT CYCLES NEWEST 10 BUS ADR DATA...

  • Page 124: Word Reads From Even And Odd Addresses

    T h e fo llo w in g list su m m a r iz e s h o w to h a n d le b r e a k s o n b y te w r ite s to e v e n an d o d d a d d r e s s e s . Assume that byte 12 is written Assume that byte 12 is written to the even address FCOO.
  • Page 125 Note that the 8086 assembler (ASM-86) reads the instruction as MOV AX, WORD PTR 0FC00. The PICE single-line assembler does not recognize the assembler operator PTR. In this case, what is a correct form for the PICE single-line assembler is an incorrect form for ASM-86.
  • Page 126 * PRINT INSTRUCTIONS NEWEST 5 MNEMONICS OPERANDS FRAME BYTE UNIT D 3F4 0063FDH 3Fb 0063FEH = ! □ 3F7 0063FFH ABObOOFC AX-.U0RD PTR DFCDDH 3FC ] 006400H 00FC00H- -DR-AB1EH 3FD 006404H ♦PRINT CYCLES NEWEST 10 DATA STATUS CLIPS 1 F RAME TIME LEVEL UNIT □...

  • Page 127: Byte Reads From Even And Odd Addresses

    The following example starts emulation from 32K using the event register. *GO FROM 32K USING oddworrf Probe 0 stopped at location DADD :0405H because of bus break Break register is ODDUORD Trace Buffer Overflow The following example checks AX to see whether the register received the word and then prints the trace buffer in INSTRUCTIONS and CYCLES modes (see Figure 3-7).
  • Page 128 34 AB SPRINT INSTRUCTIONS NEWEST 5 BYTE MNEMONICS OPERANDS UNIT 0 FRAME 3F3 00fl3FDH 3F5 0063FEH 3Fb D0fl3FFH WORD PTR 0FC01H 3F6 006400H 6B0b01FC 00FC01H-DR-AB1EH 00FC0EH-DR-5b34H 3FD □□A404H ♦PRINT NEWEST*# w m m EXEC ADR BUS ADR DATA STATUS CLIPS I F RAME TIME LEVEL UNIT 0...
  • Page 129 The following example starts emulation with this system register, displays AX, and displays the trace buffer in both INSTRUCTIONS and CYCLES mode (see Figure 3-8). Note that AX’s least significant byte has the correct value. The following example modifies the MOV instruction to read the byte from the odd address 0FC01.

  • Page 130: Moving The User Cable

    There is one memory access. The byte appears on the upper data lines. The following example defines a system register that causes a break when that condition occurs, sets AX to 0, begins emulation, and displays the trace buffer in both INSTRUCTIONS and CYCLES mode (see Figure 3-9).
  • Page 131 * DEFINE SYSREG oddbyte - * *READ AT 0FC01 1$ OABXX * A X ssO *6 0 FROM 32K USING oddbyte *Probe □ stopped at location OflOO : 0405H because of bus break Breakregister isODDBYTE Trace Buffer Overflow * PRINT INSTRUCTIONS NEWEST 5 FRAME BYTE MNEMONICS...

  • Page 133: The 8086/8088 Probe

    THE l ICE™ SYSTEM PERSONALITY MODULES (PROBES) inteT ■ ■ This chapter introduces the three PICE personality modules. (The personality modules are also referred to as probes). The 8086/8088 probe emulates the 8086 and the 8088 microprocessors. The 80186/80188 probe emulates the 80186 and the 80188 microprocessors. The 80286 probe emulates the 80286 microprocessor.

  • Page 134: Hardware And Software Considerations For The 8086/8088 Probe

    Hardware and Software Considerations for the 8086/8088 Probe This section describes the unique characteristics of the 8086/8088 probe. You should be aware of these characteristics when designing prototype hardware and software and when emulating your prototype. Separate subsections are provided on the following topics: •...

  • Page 135: Break Information

    Table 4-1 8086/8088 Segment Boundary Increments 8086/8088 Break/Trace Microprocessor Board Starting address 0:FFFFH 0FFFFH 10000H Address incremented by 1 O’ . OO OO H (next sequential address) (wrap-around) (no wrap-around) Wrap-arounds do not affect bus information, but they can make break and trace information hard to follow.

  • Page 136: Ready Signal Set-Up Time

    READY Signal Set-U p Tim e The BTHRDY (both READY) pseudo-variable ANDs the user’s processor READY signal with the 8086/8088 probe’s ready signal. When BTHRDY is TRUE, the 8086/8088 probe’s READY signal must be set up .3 nanoseconds before the rising edge of T2, as shown in Figure 4-1. If the probe processor’s READY signal is not set up .3 nanoseconds before the rising edge of T2, the signal is missed and the result of the logical AND is false.
  • Page 137 Figure 4-1 Ready Signal Set-Up Time The SYNC START/ Test Point The SYNC START/ test point is a TTL input that is normally high. When SYNC START/ is low and the probe enters emulation, READY is held low, and the probe undergoes a READY hang after the first instruction fetch.

  • Page 138: Coprocessor Considerations

    Coprocessor Considerations When using a coprocessor with the 8086/8088 probe, be aware of the following: • During emulation, a two-clock delay precedes each RQ, GT, and release pulse in MAX mode and each HOLD and HLDA assertion in MIN mode. During emulation, a user’s RQ •...

  • Page 139: 10-Mhz 8086 Probe Max Mode Operation

    10-MHz 8086 Probe MAX Mode Operation For the 8086 probe running at 10 MHz and in MAX mode, the user must supply a clock with a minimum low time of 60 nanoseconds. Less clock low time may cause a wrong address to be latched by ALE.

  • Page 140: Hardware And Software Considerations For The 80186/80188 Probe

    The PICE pseudo-variable QSTAT determines whether the 80186 probe runs in standard or queue status mode. The default is FALSE. QSTAT = TRUE The 80186 probe runs in queue status mode. QSTAT = FALSE The 80186 probe runs in standard mode. With the PICE pseudo-variables you can display and modify 80186/80188 registers and flags.

  • Page 141: Address Wrap-Around

    Address Wrap-Around The 80186/80188 microprocessor represents a memory address as a selector:offset pair. The selector and the offset are each 16 bits long. A memory address in the break/trace board is a 20-bit address. As shown in Table 4-2, the difference in memory address lengths causes discrepancies when wrap-arounds occur.

  • Page 142: Mapping Considerations For The 80186/80188 Probe

    Table 4-2 80186/80188 Segment Boundary Increments Break/Trace 80186/80188 Microprocessor Board Starting address 0:FFFFH 0FFFFH Address incremented by 1 0:0000H 10000H (next sequential address) (wrap-around) (no wrap-around) Mapping Considerations for the 80186/80188 Probe The PICE system can get out of synchronization with the 80186/80188 probe when the proto­ type system borrows slow memory or I/O from the PICE system and the user program directs the 80186/80188 microprocessor (through the probe) to ignore external READY (refer to the Chip Select/Ready Generation Logic specification in the chip literature).

  • Page 143: Synchronization Between The Prototype And The Probe

    Programming 80186/80188 internal peripheral control registers can enable the 80186/ 80188 probe processor to complete bus cycles with an internally generated READY signal while ignoring external READY. Bus cycles may be terminated with less wait- states than allowed with external READY or set by the 80186/80188 probe. The system may hang if locations that ignore external READY are not mapped to memory with the corresponding number of wait-states.

  • Page 144: User Socket

    SYNC START/ must be high for emulation to begin. User Socket Your prototype system contains a socket into which you will connect the user cable. Intel recommends using the Textool/3M socket 268-5400. See Appendix A for instructions on con­...

  • Page 145: Address Translation

    This section contains the following subsections that provide information on the 80286 micro­ processor and the 80286 probe. • Address Translation — 8086 Address Translation — 80286 Address Translation • Multitasking • Interrupts • Address Protection Real Mode and PCHECK —...
  • Page 146 The PICE system forms a physical address by shifting the selector value left by four bits and then adding the offset. The result is a 20-bit real address. With 20 bits, you can address 1M byte of memory. If you specify a physical address, you can use 24 bits even though the 8086/8088 microproces­ sor addresses 1M byte of memory.
  • Page 147 (THE LD T DESCRIPTOR M UST RESIDE IN THE GDT.) GLOBALDT TABLE INDICATOR BIT=0 ACCESS BASE LIM IT SELECTOR ACCESS BASE LIMIT GDTR BASE LIM IT Figure 4-2 The GDT and the LDT Figure 4-4 shows the relationship of the two descriptor tables (the GDT and the LDT) and the two registers (the LDTR and the GDTR).

  • Page 148: Multitasking

    G L O B A L D T LIMIT BASE ACCESS TABLE INDICATOR BIT- 0 OFFSET SELECTOR PHYSICAL ADDRESS BASE+OFFSET PHYSICAL ADDRESS BASE+OFFSET TABLE INDICATOR BIT=1 LOCAL DT ACCESS BASE LIMIT 1469 Figure 4-3 80286 Virtual Address Translation Multitasking The 80286 provides built-in multitasking support. A task switch operation saves the entire 80286 execution state (registers, address space, and a link to the previous task), loads a new execution state, and begins execution on the new task.

  • Page 149: Interrupts

    G L O B A L D T 1470 Figure 4-4 The Segment Register and the Descriptor Tables TSS command. The PICE system returns an error if you choose a selector beyond the range of the GDT or one that points to an entry in the GDT that is not a TSSD. Interrupts The 80286 contains an interrupt descriptor table (IDT) that defines up to 256 interrupts.

  • Page 150: Real Mode And Pcheck

    The PICE pseudo-variable PCHECK determines whether the PICE system operates with 80286 protection checking on or off. The default for PCHECK is TRUE. PCHECK = TRUE the PICE system observes the 80286 protection rules when view­ ing and modifying 80286 registers and accepting memory addresses.

  • Page 151: Support For Processor Extensions

    Support for Processor Extensions The PICE system with an 80286 probe supports the 80287 numeric processor extension with debugging commands. With the PICE pseudo-variables you can display and modify 80287 registers in much the same way you display and modify 8087 registers with the 8086/8088 probe.

  • Page 152: Protected Mode And Pcheck = False

    the LDTR fields directly. Changing the selector field with the LDT pseudo-variable causes the 80286 probe to update the LDTR’s explicit cache. Protected Mode and PCHECK = FALSE When the 80286 probe is in protected mode and PCHECK is FALSE, you can display and modify each LDTR field.
  • Page 153 Hardware Slipping Past a Breakpoint The are several considerations to note regarding breakpoint slipping: • Hardware slipping beyond an execution breakpoint occurs in one instance. If the instruc­ tion immediately preceding the instruction that causes the break results in an exception that occurs late in the execution cycle, the break may occur after the first instruction in the exception handling routine rather than after the expected instruction.

  • Page 154: Issuing A Reset Command When An 80287 Is Present

    tmmmwmwm T h is c o m m a n d s p e c if ie s a v ir tu a l a d d r e ss . If SEL286 = FALSE, the 80286 probe performs 8086 address translation.
  • Page 155 resume emulation, the PICE system reloads the probe’s registers with the values in the register buffer. Consequently, a RESET UNIT issued from interrogation mode does not appear to have any effect on a user program. When issued from interrogation mode, a RESET UNIT does not return the probe’s micropro­ cessor to real mode.

  • Page 156: Resetting The 80286 Chip And The 80286 Probe

    The RESET ICE command also returns the AX, BX, CX, and DX registers, the stack and base pointers, and the source and destination indexes to the same values that the 80286 registers have after reset. Resetting the 80286 Chip and the 80286 Probe The system clock provides the fundamental timing for the 80286 system.

  • Page 157: Tracing Considerations

    User Socket Your prototype system contains a socket into which you will connect the user cable. Intel recommends using the Textool/3M socket 268-5400. See Appendix A for instructions on con­...

  • Page 158: Reading From And Mapping To Mapped Memory Or I/O

    A problem arises if you try to load the initialization segment with the PICE system 8086 loader (your program is an 8086 OMF). Protected-mode users should construct 80286 OMFs and hence use the 80286 loader. If you still need to load the initialization segment with the 8086 loader, one method is to first map the initialization segment to where you want the initialization code to reside.

  • Page 159: Coprocessor Support

    COPROCESSOR SUPPORT iny " A coprocessor is a microprocessor that enhances the functions of the CPU. The 8087 and 80287 numeric data processors (NDP) perform arithmetic and comparison oper­ ations on a variety of numeric data types as well as executing numerous built-in transcendental functions.

  • Page 160: The Coenab Pseudo-Variable

    The PICE commands provide access to the 8087’s and 80287’s stack, status registers, and flags. The PICE system’s disassembly and trace features extend to 8087 and 80287 instructions and data types. How the PICE system treats the 8087 depends on the two pseudo-variables COENAB and CPMODE and on the GET87 command.

  • Page 161: Coenab And An External Coprocessor

    For the 8086/8088 and 80186/80188 probes, COENAB’s default value is TRUE. For the 80286 probe, COENAB’s default value is FALSE. Note that, for the 8086/8088 and 80186/ 80188 probes, when the PICE software is invoked, it checks the request/grant or hold/hold acknowledge lines before the COENAB pseudo-variable’s default value is set.

  • Page 162: The Coreq Pseudo-Variable

    The COREQ Pseudo-Variable The COREQ pseudo-variable enables or disables an external numeric extension and is specific to the 80286 probe. When COREQ = TRUE, the 80286 probe recognizes its PEREQ and PEACK lines. Setting COREQ = FALSE disables the external numeric extension, and the 80286 probes does not recognized the PEREQ and PEACK lines.

  • Page 163: Multiple-Probe Systems

    MULTIPLE-PROBE SYSTEMS This chapter describes the operation of a multiple-probe PICE system. It introduces the PICE commands that control the system break and trace lines and explains how to arm the PICE system, assert the system break and trace lines, enable a unit, and write debug procedures for use with multiple probes I2ICE™...

  • Page 164: Arming The Pice™ System

    Figure 6-1 A Multiple-Probe PICE™ System Arming the PICE™ System The PICE system is armed by default. You can arm and disarm the PICE system with the following: • The SYSTEM ARM/DISARM command. • An event specification—you can specify the keyword SYS ARM in an event register or in the GO command.

  • Page 165: Asserting The System Break And Trace Lines

    Asserting the System Break and Trace Lines You can assert the system break line with an event specification or a system specification. You can specify the keyword SYSTRIG (for asserting the system break line) or the keyword SYSTRACE (for asserting the system trace line) in an event register, system register, or in the GO command.

  • Page 166: Symbolic Support For Multiple Probes

    The following example deals with two units. Unit 0 arms the system when its program executes statement #12. Unit 1 triggers the system when its program executes statement #22. Unit 0 and unit 1 recognize the system trigger line and break when it is asserted. * \0 ENABLE SYSBREAK1N * \ 1 ENABLE SYSBREAKIN * DEFINE SYSRE6 armO = SYSARM AT ;cmaker#12...

  • Page 167: Writing Debug Procedures For Multiple Probe Systems

    The following example illustrates inter-probe communication. Assume that unit 0 and unit 1 are emulating a program (progO for unit 0 and progl for unit 1) and that you want unit 0 to break when unit 1 writes a variable called pvarl. You do not want unit 1 to break. ^SYSTEM ARM *\GENABLE SYSBREAKIN * V1 DISABLE SYSBREAKIN...

  • Page 168: Synchronization Between Units

    . . *IF (WAIT = = 0) OR (WAIT = =255T) THIN . . . *GO TIL WRITE AT 0031H:000EH . . . *£ND . . *1NI1 . *END WAIT is also useful in single-probe systems when, for example, the program runs for a long time before breaking.

  • Page 169: The 80286 Probe

    of the two clipsout lines. These are output from the PICE system and are initially low. Then, enter the GO command for each probe. Each probe hangs after the first instruction fetch. Then, set the clipsout line to 1. All the probes enter emulation simultaneously. The 80286 Probe SYNC START/ is normally high.

  • Page 171: The Pice™ System Instrumentation Chassis Installation

    PICE™ SYSTEM NON-HOST HARDWARE INSTALLATION intel ■ ■ The hardware installation procedure for the PICE system depends on the host development system, the number of PICE chassis in the system, and the system options. Begin installation of your PICE system using the installation instructions in this appendix. The appendix has sections on the following host-independent topics.
  • Page 172 1149 Figure A -l Power Cable 3. If the system location is in an area where the power outlets do not match the power plug on the instrumentation chassis power cord, remove the power plug and install the appropriate power connector. Refer to Figure A-l when installing a new power connector.
  • Page 173 i3" SYSBRK OUT ICE-LINK OUT S5 | TERMINATION SWITCHES LAST OR ONLY UNIT ON POSITION ALL OTHER UNITS OFF POSTION 1150 Figure A-3 Termination Switches on the Rear Panel of the PICE™ System Instrumentation Chassis To avoid overloading the line circuit, ensure that each PICE instrumentation chassis is on a separate line circuit and that the host development system is on a separate line circuit.

  • Page 174: Emulation Base Module Installation

    Emulation Base Module Installation The emulation base module consists of a break/trace board, a map-I/O board, the buffer base assembly, and an emulation clips module. The break/trace board, the map-I/O board, and the buffer base assembly are already installed. Figure A-4 shows the location of the break/trace board and the map-I/O board in the PICE instrumentation chassis.
  • Page 175 E1-E2 JUMPERED FOR NORMAL OPERATION. E3-E4 1201 Figure A-5 Jumper Positions on the Map-I/O Board PICE™ System Non-Host Hardware Installation A -5...
  • Page 176 FOR T H E 8 0 8 6 / 8 0 88 P R O B E, TH E S E C A B L E S M U S T BE R E P LAC ED . SEE T H E 8 0 8 6 /8 0 8 8 PR O B E IN S T A LL A T IO N S E C T IO N .

  • Page 177: Jumpering For 8087 Support

    Table A-2 Jumpering for 8087 Support Jumpers Location of Coprocessor User Plug NMI Source user system from user system E1-E2 E19-E20 internal E28-E29 coprocessor from 8087 INTR E1-E2 E20-E21 E28-E29 loopback none E1-E2 E28-E29 E19-E20 from 8087 INTR E1-E2 E20-E21 E28-E29 no internal from user system...
  • Page 178 Figure A-8 8086/8088 Emulation Personality Module Installation The two cables that you will replace connect the two halves of the probe buffer box. One half of the buffer box contains the probe buffer board (the words “ PROBE BUFFER” are silk-screened on it);...
  • Page 179 d) Bend the other end of the cable so that you can insert it at J2 of the personality board. e) Repeat steps 3 and 4 for the second cable, connecting the cable from J5 of the probe buffer to J1 of the personality board. 2.

  • Page 180: Installing The 8086/8088 User Cable

    5. If your emulator configuration calls for an 8087 processor used as an internal coprocessor, perform the following steps to install the iSBC 337 MULTIMODULE board in the U52 socket of the personality board. See Figure A-9. Remove the 8086 or 8088 microprocessor from the socket at U52. b.

  • Page 181: Installing The Pice™ System 80186/80188 Emulation Personality Module

    10.9" BUFFER 1211 Figure A-10 8086/8088 User Cable Dimensions incorrectly (see Figure A -l 1). On some versions a dot identifies the position on the buffer box socket that is intended to contain pin 1 of the user cable. Connect the cable to the top of the buffer box now;...
  • Page 182 U 19 socket of the personality board. Note that this is a bond-out chip available only from Intel. The U 19 socket is on the personality board; the PGA socket on top of the buffer box is reserved for the user cable in loopback mode.
  • Page 183 Figure A-12 80186/80188 and 80286 Emulation Personality Module Installation E1 7-E1 8 for 1 6-bit emulation (8 0 1 8 6 ) E1 6-E1 7 for 8-bit emulation (801 88) Figure A-13 Jum per Positions on the 80186/80188 Personality Board ™...

  • Page 184: Installing The 80186/80188 User Cable

    Installing the 80186/80188 User Cable When you are first learning about the PICE system, you will want to have the user cable looped back to the top of the buffer box for use with the PICE tutorial. Later, when you are ready to connect your probe to your prototype hardware (also called target hardware), return to this section for information on connecting the user cable to prototype hardware.
  • Page 185 80186/80188 user cable. NOTE When you use the 80186/80188 or 80286 probe, Intel recommends that the prototype contain the Textool/3M socket 268-5400. If you have multiple PICE chassis, install the emulation clips on the other chassis.

  • Page 186: Installing The Pice™ System 80286 Emulation Personality Module

    Installing the PICE™ System 80286 Emulation Personality Module The 80286 emulation personality module consists of the two 80286 personality boards, the user and ground clip cables, and the 80286 buffer box cover. The 80286 emulation personality module connects to the buffer base assembly and configures the generic portion of the PICE system to emulate a specific processor.
  • Page 187 0.116 inches. If you retain the PGA socket at the end of the cable, even the A orientation may require an empty slot. NOTE When you use the 80186/80188 or 80286 probe, Intel recommends that the prototype contain the TextooI/3M socket 268-5400. This completes installation of the 80286 probe. If you have no other personality modules to install, go now to the emulation elips installation section.

  • Page 188: Installing The Emulation Clips Module

    Installing the Emulation Clips Module After your personality modules are installed, perform the following steps to install the emula­ tion clips module. 1. Connect the terminator assembly to the emulation clips module (P2 to J2) (see Figure A-17). 2. Install as many microhooks as needed for the system on the wires of the terminator assem­ bly (see Figure A-17).
  • Page 189 Figure A-18 Instrumentation Chassis Cables PICE™ System Non-Host Hardware Installation A -1 9...

  • Page 190: Installing The Ilta Logic Timing Analyzer Option

    If you have an IBM PC host, refer now to Appendix C. If you have an Intel host you did not receive the Appendix C for IBM PC hosts. Instead, you received Appendixes C through G that concern Intel hosts.
  • Page 191 Table A-3 Intel Host Installation Appendixes Hardware Installation Software Installation Your Host Appendix Appendix Model 800 Stand-alone Series III Series III on a Network Series IV PICK™ System Non-Host H ardware Installation A-2 l/A-22...

  • Page 193: Creating A Crt File

    ICE™ SYSTEM FOR NON-STANDARD HOST TERMINALS The PICE system is designed to run on either an Intel host development system with a standard Intel CRT or on an IBM PC/AT or PC/XT with a standard terminal. The codes expected from the terminal or sent to the terminal are those used by standard Intel or IBM terminals.

  • Page 194: Configuration Commands

    • The PICE software automatically generates a linefeed each time the carriage return is entered. The terminal should not generate a linefeed with a carriage return. In some termi­ nals, this function can be switched on and off. Configuration Commands Configuration commands modify the environment and the communication link between PICE software and the keyboard and the screen.
  • Page 195 Table B -l The A Configuration Command Values Series III & IBM PC* Series IV A code Defaults Defaults Description ESCAPE — a new value should be assigned for terminals that require the ESCAPE key for control sequences. The offset value to be added to the row and column numbers following the cursor control sequence of the AF command AFAC.

  • Page 196: The Af Configuration Command Values

    Table B-2 The AF Configuration Command Values Series III & IBM PC* Series IV AFcode Defaults Defaults Description The setting has no effect until cursor addressing mode is set with the AF command, AFAC. 1B19 Code used as the cursor movement command AFAC by the terminal.
  • Page 197 Code to move the cursor to the right. AFMU 1B01 Code to move the cursor up. AFTM CTRL-V — this command is unique to l2ICE systems. It sets the control character that enables you to turn the menu display on and off. AFXA CTRL-A — delete right.
  • Page 199 GLOSSARY ■ ■ ■ ■ ■ ■ in te rs Address An address is an unsigned value that corresponds to a location in pro­ gram memory. The PICE system recognizes absolute addresses, virtual addresses, and symbolic references to addresses. The arm condition is an optional part of a break/trace sequence in the PICE system.
  • Page 200 Forcing Character The forcing character in the PICE command syntax is the double-quote (") unary operator. When the forcing character precedes a keyword, the PICE system interprets the keyword as a user program symbol. History Buffer A buffer that stores recent commands. The commands can be recalled using the up-arrow key.
  • Page 201 Syntax Menu A menu at the bottom of the screen that indicates what command ele­ ments are legal during command entry. Tracing The PICE system keeps a record of trace information each time it enters emulation. Unary Operator A unary operator is an operator that acts on a single operand. The PICE system recognizes the NOT, + , —, and .
  • Page 203 INDEX inteT $ pseudo-variable, 3-30 * high-address-bits override, 4-21 * prompt, 2-3, 3-3, 3-28 + 5-volt source and user substrate capacitor, 80286 probe, 4-24 \ (backslash) command, 6-1, 6-3 10-MHz 8086 probe MAX mode operation, 4-7 87 INT test point, 4-5 8086 environment, 1-12 8086/8088 personality board jumper positions, A-9 8086/8088 personality module (probe): 4-1...
  • Page 204 80286/8086: address translation, 4-21, 4-22 loader, 4-25 80287 numeric processor extension, 4-19, 4-22, 5-1 82188 coprocessor interface chip, 5-1 Aborting commands, 3-3 Access codes, 3-39 Accessories of the PICE system, 1-7 Address/data (AD) bus float, 8086/8088 probe, 4-7 ADDRESS memory type, 3-15 Address: even and odd, 3-44 thru 3-55 protection, 80286 probe, 4-17...
  • Page 205 3-51 writes from even and odd addresses, 3-47 Byte-wide ports, 3-22, 3-24 Cable, internal host installation, see Intel host hardware installation appendix Cables, system interface, 1-11 Cascade interrupt address, 80286 probe, 4-24 CAUSE command, 6-6...
  • Page 206 Concatenating strings, 3-6 Confidence tests: see host hardware installation appendix commands, see host hardware installation appendix messages and flags, see host hardware installation appendix Configuration commands, B-2 Configuration file, see software installation appendix Configuration of the PICE system, 1-4 Configuring the PICE system for non-standard host terminals, B-l Continuing commands to another line, 3-3 Conventions, syntax, xiv Converting memory types, 3-6...
  • Page 207 DIR command, 3-31 DO-END block, 3-7, 3-8 DOS operating system, 1-14 DT/R signal, 8086/8088 probe, 4-7 DWORD memory template, 3-15 EDIT command, 3-10 Editing external files, 3-11 Editors, 3-4, 3-10 Emulating programs, 3-28, 3-30, 3-34 Emulation: base module, 1-10 base module installation, A-4 break, reason for, 6-6 buffer board, 1-10 clips, 1-05, 1-7, 3-25...
  • Page 208 File: editing, external, 3-11 handling, 3-12 handling commands, 1-14 Final hardware checkout, see host hardware installation appendix Flags and registers, 80286 probe, 4-19 Fully qualified references, 3-17 Functions, 1-14 GET87 command, 5-2, 5-3, 5-4 Global descriptor table (GDT) for the 80286 probe, 4-14, 4-16, 4-17 GO command, 3-30 thru 3-32, 3-34, 3-44 thru 3-53, 6-2, 6-3 GRANULARITY pseudo-variable, 80286 probe, 4-18, 4-26 Guarded memory, 3-19, 4-18...
  • Page 209 A-l INTA signal, 8086/8088 probe, 4-7 INTEGER memory template, 3-15 Integrating hardware and software, 1-3 Intel Logic Timing Analyzer (iLTA): 1-3, 1-6, 1-11 disks, 1-16 Intellec Series III: confidence tests, see Series III hardware installation appendix configuration requirements, 1-18...
  • Page 210 Interface cables, 1-11 Interface chip, 5-1 Internal coprocessors, 5-1, 5-3, 5-4 Internal host cable installation, see Intel host hardware installation appendix Inter-probe communication, 6-5 Interrogation mode: 80286 probe, 4-22 8086/8088 probe, 4-6 Interrupt line (INTR), 8086/8088 probe, 4-4...
  • Page 211 Map-I/O board, 1-4, 1-10 MAPIO command, 3-21 thru 3-24, 3-29 Mapping considerations, 80186/80188 probe, 4-10 Mapping I/O: 3-21 thru 3-24, 3-29 80286 probe, 4-26 Mapping memory: 3-19, 3-29 80286 probe, 4-18,4-26 MAX mode, 8086/8088 probe, 4-6, 4-7 Memory access time-out, 3-34 Memory management, 3-19 Memory mapping: 3-19 80186/80188 probe, 4-10...
  • Page 212 breaking, 3-44 byte reads, 3-51 byte writes, 3-47 word reads, 3-48 word writes, 3-44 OHS memory, see optional high-speed memory Operating systems, 1-12 Optional high-speed (OHS) memory, 1-11, 3-19, 4-18 Options of the PICE system, 1-6 Partially qualified references, 3-18 Pathname, 3-12 PCHECK pseudo-variable: 4-17, 4-19, 4-20 80286 probe, 4-21...
  • Page 213 8086/8088 probe, 4-4 80186/80188 probe, 4-11 PSCOPE-86: disk, 1-16 software, 1-6 Pseudo-variables, 1-15 Publications, PICE system, xii Pulse stretching, ALE (80186/80188 probe), 4-12 PUT command, 3-13, 3-32 QSTAT pseudo-variable, 4-8 Read-after-write verification, 3-20 Read-only memory, 3-20 READY hang, 6-6 READY signal: 3-21 set-up time, 8086/8088 probe, 4-4 80186/80188 probe, 4-10 thru 4-12 REAL memory template, 3-15...
  • Page 214 SAVE command, 3-14 Saving debug object definitions, 3-32 Screen editor, 3-10 Segment boundary increments: 8086/8088 probe, 4-3 80186/80188 probe, 4-10 SEL286 pseudo-variable, 80286 probe, 4-13, 4-21, 4-22 SELECTOR memory template, 3-15 Selector:selector:offset triplet, 80286 probe, 4-22 SEM, 3-35 Series III, see Intellec Series III Series IV, see Intellec Series IV Service and repair assistance, xix Set-up time for the READY signal, 8086/8088 probe, 4-4...
  • Page 215 packaging, 1-15 Software/hardware integration, 1-3 Source file compilation, 3-27 Specifications, FICE system, 1-17 STATUS command, 80286 probe, 4-23 Stepping through user programs, 8086/8088 probe, 4-4 String handling, 3-6 Submit file, 3-27 SUBSTR function, 3-6 Substrings, 3-6 Symbolic: debugging, 3-16 display, 3-31 support for multiple probes, 6-4 SYNC START test point: 6-6, 6-7 80186/80188 probe, 4-11, 4-12...
  • Page 216 80286 probe, 4-25 TIMEBASE pseudo-variable, 3-42 Time-out pseudo-variables, 3-34, 5-1 Time-outs: MEMRDY, 80186/80188 probe, 4-11 Timetags, 3-42 Timing differences between 80286 probe and 80286 chip, 4-24 Timing differences between probes and chips, 1-19 TP test point, 80186/80188 probe, 4-11 Trace: and break lines, 3-26, 6-1, 6-2 buffer, 2-5, 3-38, 3-42 buffer display, 8086/8088 probe, 4-6...
  • Page 217 User memory, 3-19, 4-18, 5-1 User plug, 8086/8088 probe, A -10 User socket: 80186/80188 probe, 4-12, A-14 80286 probe, 4-25 User substrate capacitor and + 5-volt source, 80286 probe, 4-24 User-accessible test points: 8086/8088 probe, 4-4 80186/80188 probe, 4-11 80286 probe, 4-25 Utility commands, 1-14 Variables, 3-16 thru 3-18 Virtual address translation for the 80286 probe, 4-13, 4-14...
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