Intel l2ICE User Manual page 8

Non-Maskable Interrupt Line and Interrupt Line....................................................................... 4-4
Non-Maskable Interrupts and Program Stepping....................................................................... 4-4
Synchronization between the Prototype and the P ro b e ............................................................. 4-4
User-Accessible Test P o in ts......................................................................................................... 4-4
Coprocessor Considerations......................................................................................................... 4-6
Inability to Break when RESET Is A sserted .............................................................................. 4-6
Getting a User NMI while in Emulation Mode
Using the PICE™ System as a Signal G enerator....................................................................... 4-6
10-MHz 8086 Probe MAX Mode O peration............................................................................. 4-7
Probe MIN Mode Operation......................................................................................................... 4-7
Address/Data Bus F lo a t............................................................................................................... 4-7
The 80186/80188 P ro b e ....................................................................................................................... 4-7
Hardware and Software Considerations for the 80186/80188 P ro b e .......................................... 4-8
Address Wrap-Around................................................................................................................... 4-9
Break Information......................................................................................................................... 4-9
Mapping Considerations for the 80186/80188 P ro b e ............................................................... 4-10
Synchronization Between the Prototype and the P ro b e............................................................. 4-11
User-Accessible Test P o in ts......................................................................................................... 4-11
User S ocket.................................................................................................................................... 4-12
The 80286 P ro b e.................................................................................................................................... 4-12
Address Translation............................................................................................................................ 4-13
8086 Address Translation............................................................................................................. 4-13
80286 Address Translation........................................................................................................... 4-14
Multitasking........................................................................................................................................ 4-16
Interrupts............................................................................................................................................ 4-17
Address P rotection............................................................................................................................ 4-17
Real Mode and PCH ECK ............................................................................................................. 4-18
Protected Mode and PC H EC K ..................................................................................................... 4-18
Memory Mapping for the 80286 P ro b e ........................... ........................................................ ..
Support for Processor Extensions..................................................................................................... 4-19
Displaying 80286 Registers and F lag s............................................................................................ 4-19
Real Mode and PCHECK = TRUE.............................................................................................. 4-19
Real Mode and PCHECK = FALSE............................................................................................ 4-19
Protected Mode and PCHECK = TRUE...................................................................................... 4-19
Protected Mode and PCHECK = FALSE.................................................................................... 4-20
Hardware and Software Considerations for the 80286 P ro b e ....................................................... 4-20
Hardware Slipping Past a Breakpoint............................................................................. ............ 4-21
High-Address Bits O verride......................................................................................................... 4-22
Issuing a Reset Command When an 80287 Is Present............................................................... 4-22
Resetting the 80286 Chip and the 80286 P ro b e......................................................................... 4-24
Timing Differences Between the iAPX 286 and the 80286 P ro b e .......................................... 4-24
User Substrate Capacitor and + 5 Volt S ource........................................................................... 4-24
Tracing Considerations................................................................................................................. 4-25
User Socket.................................................. ............................................................ .................... 4-25
Synchronizing Emulation to an External E v en t......................................................................... 4-25
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................................................................. 4-6
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