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2: PINS
2.1.2
Pin Description
Key :
I
=
O
=
IO
=
P
=
HIBC
=
HIBH
=
HIBCD1 =
HOB2T
=
HBC2T
=
HTB2T
=
HLIN
= Transparent input
HLOT
= Transparent output
ITST1
=
Pin Name
HIOVDD(V
)
7 • 48 • 55
DD
NIOVDD(V
)
22 • 32
DD
COREVDD(V
)
12 • 25 • 40
DD
V
1 • 17 • 28 • 33 • 53
SS
CLKI
39
XCG1(XG)
35
XCD1(XD)
34
CNF0 – CNF4
56-60
(SEL0 – SEL4)
DB0 – DB7
44-47 • 49-52
(D0 – D7)
AB0 – AB15
2-6 • 8-11 • 13-16
(A0 – A15)
RD#
41
WR#
42
CS#
43
WAIT#
54
AS#
61
FPDAT0 –
18-21
FPDAT3(XD0 – XD3)
FPSHIFT(XSCL)
23
XECL
24
FPLINE(LP)
26
MOD(WF)
27
YSCL
29
FPFRAME (YD)
30
6
Input
Output
Input/output
Power supply
CMOS input
CMOS Schmitt input
CMOS input with pulldown resistor (60 ohms typ. at 5.0 V)
Normal buffer (8 mA/-8 mA at 5 V)
LVTTL I/O buffer (6 mA/-6 mA at 3.3 V)
Tri-state output (6 mA/-6 mA at 3.3 V)
Test mode control input with pulldown resistor (50 ohms typ. at 3.3 V)
I/O
Pin No.
Type
P
P
P
P
I
I
O
I
IO
I
I
I
I
O
I
O
O
O
O
O
O
O
I/O Voltage
I/O Cell
HIOVDD
—
NIOVDD
—
COREVDD
—
V
—
SS
HIOVDD
HIBH
HIOVDD
HLOT
HIOVDD
HLIN
HIOVDD
HIBH
HIOVDD
HBC2T
HIOVDD
HIBC
HIOVDD
HIBH
HIOVDD
HIBH
HIOVDD
HIBH
HIOVDD
HOB2T
HIOVDD
HIBC
NIOVDD
HOB2T
NIOVDD
HOB2T
NIOVDD
HOB2T
NIOVDD
HOB2T
NIOVDD
HOB2T
NIOVDD
HOB2T
NIOVDD
HOB2T
EPSON
RESET#
Description
State
—
Power supply for host interface
—
Power supply for LCD interface
—
Power supply for core logic
—
Ground
—
Externally sourced system clock
—
Gate input for oscillator
—
Drain output for oscillator
0
Input pin for S1D13700 settings
Hi-Z
Data bus for MPU interface
0
Address bus for MPU interface
1
Read strobe for MPU interface
1
Write strobe for MPU interface
1
Chip select for MPU interface
Hi-Z
Wait output for MPU interface
Address strobe for MPU
1
interface
X
Data bus for X driver
X
Shift clock for X driver
X
X driver enable chain clock
X
Latch pulse
X
Frame signal
X
Scan shift clock
X
Scan start pulse
S1D13700 Technical Manual
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