Part 6.4: Usb2.0 Interface - Alinx ZYNQ 7000 User Manual

Part 6.4: USB2.0 Interface

There are 1 USB2.0 HOST interfaces on the AX7020 FPGA development
board. The USB2.0 transceiver uses a 1.8V, high-speed USB3320C-EZK chip
that supports the ULPI standard interface. ZYNQ's USB bus interface is
connected to the USB3320C-EZK transceiver for high-speed USB2.0 Host
mode and Slave mode data communication. The USB3320C's USB data and
control signals are connected to the IO port of the BANK501 on the PS side of
the ZYNQ chip. One 24MHz crystals provide clocks for the USB3320C.
The AX7020 FPGA development board provides users with two USB
interfaces, one is the Host USB port and the other is the Slave USB port. They
are a flat USB interface (USB Type A) and a micro USB interface (Micro USB),
which are convenient for users to connect different USB peripherals. Users can
switch between Host and Slave through J5 and J6 jumpers on the AX7020
FPGA development board. Table 6-4 shows the mode switching instructions:
J5,J6 Status
J5 and J6 installation
jumper caps
J5 and J6 not
installation jumper
caps
Figure 6-6: The connection between Zynq7000 and USB chip
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ZYNQ FPGA Development Board AX7020 User Manual
USB Mode
HOST Mode FPGA Development board as the main device, USB
port to connect the mouse, keyboard, USB and other
OTG/Slave Mode FPGA Development board as a slave device, USB port
Table 6-4: The mode Switching Instructions
Instruction
slave peripherals
to connect to the computer