Part 6.3: Gigabit Ethernet Interface - Alinx ZYNQ 7000 User Manual

DDR3_A[6]
DDR3_A[7]
DDR3_A[8]
DDR3_A[9]
DDR3_A[10]
DDR3_A[11]
DDR3_A[12]
DDR3_A[13]
DDR3_A[14]
DDR3_BA[0]
DDR3_BA[1]
DDR3_BA[2]
DDR3_S0
DDR3_RAS
DDR3_CAS
DDR3_WE
DDR3_ODT
DDR3_RESET
DDR3_CLK_P
DDR3_CLK_N
DDR3_CKE

Part 6.3: Gigabit Ethernet Interface

The Ethernet chip uses Realtek's RTL8211E-VL Ethernet PHY chip to
provide network communication services to users. The Ethernet PHY chip on
the PS side is connected to the GPIO interface of the BANK501 of the PS side
of ZYNQ. The RTL8211E-VL chip supports 10/100/1000 Mbps network
transmission rate and communicates with the MAC layer of the Zynq7000 PS
system through the RGMII interface. RTL8211E-VL supports MDI/MDX
adaptation, various speed adaptation, Master/Slave adaptation, and supports
MDIO bus for PHY register management.
The RTL8211E-VL power-on will detect the level status of some specific
IOs to determine their working mode. Table 6-3 describes the default setup
information after the GPHY chip is powered up.
24 / 47
ZYNQ FPGA Development Board AX7020 User Manual
PS_DDR_A6_502
PS_DDR_A7_502
PS_DDR_A8_502
PS_DDR_A9_502
PS_DDR_A10_502
PS_DDR_A11_502
PS_DDR_A12_502
PS_DDR_A13_502
PS_DDR_A14_502
PS_DDR_BA0_502
PS_DDR_BA1_502
PS_DDR_BA2_502
PS_DDR_CS_B_502
PS_DDR_RAS_B_502
PS_DDR_CAS_B_502
PS_DDR_WE_B_502
PS_DDR_ODT_502
PS_DDR_DRST_B_502
PS_DDR_CKP_502
PS_DDR_CKN_502
PS_DDR_CKE_502
L4
K4
K1
J4
F5
G4
E4
D4
F4
L5
R4
J5
N1
P4
P5
M5
N5
B4
L2
M2
N3