Alinx ZYNQ 7000 User Manual page 26

Figure 6-5: The GPHY chip on FPGA Board
The Gigabit Ethernet pin assignments are as follows：
Signal Name
ETH_GCLK
ETH_TXD0
ETH_TXD1
ETH_TXD2
ETH_TXD3
ETH_TXCTL
ETH_RXCK
ETH_RXD0
ETH_RXD1
ETH_RXD2
ETH_RXD3
ETH_RXCTL
ETH_MDC
ETH_MDIO
26 / 47
ZYNQ FPGA Development Board AX7020 User Manual
ZYNQ Pin Name
PS_MIO16_501
PS_MIO17_501
PS_MIO18_501
PS_MIO19_501
PS_MIO20_501
PS_MIO21_501
PS_MIO22_501
PS_MIO23_501
PS_MIO24_501
PS_MIO25_501
PS_MIO26_501
PS_MIO27_501
PS_MIO52_501
PS_MIO53_501
ZYNQ Pin Number
A19
E14
B18
D10
A17
F14
B17
D11
A16
F15
A15
D13
C10
C11
Description
RGMII Transmit Clock
Transmit data bit0
Transmit data bit1
Transmit data bit2
Transmit data bit3
Transmit enable signal
RGMII Receive Clock
Receive data Bit0
Receive data Bit1
Receive data Bit2
Receive data Bit3
Receive data valid signal
MDIO Management clock
MDIO Management data