Alinx ZYNQ 7000 User Manual page 22

Figure 6-3: Two DDR3 DRAMs on the FPGA Board
DDR3 Pin Assignment:
Signal Name
DDR3_DQS0_P
DDR3_DQS0_N
DDR3_DQS1_P
DDR3_DQS1_N
DDR3_DQS2_P
DDR3_DQS2_N
DDR3_DQS3_P
DDR3_DQS4_N
DDR3_DQ[0]
DDR3_DQ [1]
DDR3_DQ [2]
DDR3_DQ [3]
DDR3_DQ [4]
DDR3_DQ [5]
22 / 47
ZYNQ FPGA Development Board AX7020 User Manual
ZYNQ Pin Name
PS_DDR_DQS_P0_502
PS_DDR_DQS_N0_502
PS_DDR_DQS_P1_502
PS_DDR_DQS_N1_502
PS_DDR_DQS_P2_502
PS_DDR_DQS_N2_502
PS_DDR_DQS_P3_502
PS_DDR_DQS_N3_502
PS_DDR_DQ0_502
PS_DDR_DQ1_502
PS_DDR_DQ2_502
PS_DDR_DQ3_502
PS_DDR_DQ4_502
PS_DDR_DQ5_502
ZYNQ Pin Number
C2
B2
G2
F2
R2
T2
W5
W4
C3
B3
A2
A4
D3
D1