Alinx ZYNQ 7000 User Manual page 25

Configuration Pin
PHYAD[2:0]
SELRGV
AN[1:0]
RX Delay
TX Delay
When the network is connected to Gigabit Ethernet, the data
transmission of ZYNQ and PHY chip
RGMII bus, the transmission clock is 125Mhz, and the data is sampled on the
rising edge and falling samples of the clock.
When the network is connected to 100M Ethernet, the data transmission of
ZYNQ and PHY chip
transmission clock is 25Mhz. Data is sampled on the rising edge and falling
samples of the clock.
Figure 6-4: The connection of the ZYNQ and GPHY chip
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ZYNQ FPGA Development Board AX7020 User Manual
Instructions
MDIO/MDC Mode PHY Address
RGMII 1.8V or 1.5V level selection
Auto-negotiation configuration
RX clock 2ns delay
TX clock 2ns delay
Table 6-3: PHY chip default configuration value
is communicated through RMII bus, and the
RTL8211E-VL
Configuration value
is communicated through the
RTL8211E-VL
PHY Address 为 001
1.8V
10/100/1000 adaptive
Delay
Delay