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Alinx AV6150 User Manual

Fpga video processing development platform
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FPGA Video Processing
Development Platform
AV6150
User Manual

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  • Page 1 FPGA Video Processing Development Platform AV6150 User Manual...

  • Page 2: Version Record

    FPGA Video Processing Development Platform AV6150 User Manual Version Record Version Date Release By Description Rev 1.0 2019-05-01 Rachel Zhou First Release 2 / 55 Contact Email: rachel.zhou@alinx.com.cn...

  • Page 3: Table Of Contents

    FPGA Video Processing Development Platform AV6150 User Manual Table of Contents Version Record ..................2 Part 1: FPGA Development Board Introduction ......... 6 Part 2: Function realization ................ 8 Part 2.1: Video Input ................8 Part 2.2: Video Output ............... 11 Part 3: AC6150 core board ..............
  • Page 4 FPGA Video Processing Development Platform AV6150 User Manual Part 4.10: JTAG Interface ..............52 Part 4.11: Buttons ................53 Part 4.12: Power Supply ..............54 4 / 55 Contact Email: rachel.zhou@alinx.com.cn...
  • Page 5 FPGA Video Processing Development Platform AV6150 User Manual This XILINX FPGA Video Processing development platform (module: AV6150) adopts the core board + carrier board mode, which is convenient for users to use the core board for secondary development. This FPGA video image processing development platform is derived from the improvement of our company's ALTERA video development board.

  • Page 6: Part 1: Fpga Development Board Introduction

    FPGA Video Processing Development Platform AV6150 User Manual Part 1: FPGA Development Board Introduction The entire structure of the AV6150 FPGA development board is inherited from our consistent core board + carrier board model. A high-speed inter-board connector is used between the core board and the carrier board.
  • Page 7 FPGA Video Processing Development Platform AV6150 User Manual 视频 视频 视频 视频 HDMI输出 HDMI输入 VGA输出 输入 输入 输入 输入 接口 接口 接口 接口 ADV7123 SiI9134 TW2867 SiI9013 XILINX XC6SLX45 CP2102 RTL8211E 以太网网 CMOS接口 USB UART SD Card 口 Figure 1-1-1: The Schematic Diagram of the AV6150...

  • Page 8: Part 2: Function Realization

    FPGA Video Processing Development Platform AV6150 User Manual  1-channel HDMI Output Select Silion Image SIL9134 HDMI encoding chip, support up to 1080P@60Hz output, support 3D output.  1-channel HDMI Input Select Silion Image SIL9013 HDMI decoder chip, support up to 1080P@60Hz input, support different formats of data output ...
  • Page 9 FPGA Video Processing Development Platform AV6150 User Manual 1) Surveillance cameras Through the FPGA development board, it is possible to realize four-channel surveillance camera through the display (VGA/DVI/HDMI interface, which can realize 1080p) for split-screen display. Our development board is equivalent to the digital video host in the Figure below.
  • Page 10 FPGA Video Processing Development Platform AV6150 User Manual Figure 2-1-2: Set top box 3) Camera Module CMOS camera interface, plug in ALINX 30 megapixel camera module or 5 megapixel camera module, real-time display 1080P video image on VGA display or HDMI display.

  • Page 11: Part 2.2: Video Output

    FPGA Video Processing Development Platform AV6150 User Manual Part 2.2: Video Output There are two kinds of video output on the FPGA development board: you can connect a VGA monitor to display VGA images; you can also connect HMDI monitors or TV to display HDMI video signals. The video display for VGA and HDMI output is up to 1080P@60Hz.

  • Page 12: Part 3: Ac6150 Core Board

    FPGA Video Processing Development Platform AV6150 User Manual Part 3: AC6150 core board 12 / 55 Contact Email: rachel.zhou@alinx.com.cn...

  • Page 13: Part 3.1: Ac6150 Core Board Introduction

    FPGA Video Processing Development Platform AV6150 User Manual Part 3.1: AC6150 Core Board Introduction FPGA+ DDR3 core board is based on XILINX's SPARTAN6 series XC6SLX150-2FG484C. This chip develops a high-performance core board with high speed, high bandwidth and high capacity. It is suitable for video image processing and high-speed data acquisition.
  • Page 14 FPGA Video Processing Development Platform AV6150 User Manual Figure 3-2-2: FPGA chip on the core board The main parameters of the FPGA chip XC7A100T are as follows Name Specific parameters Logic Cells 147,443 Slices 23038 CLB flip-flops 184,304 4,824 Block RAM（kb）...

  • Page 15: Part 3.3: Ddr3 Dram

    FPGA Video Processing Development Platform AV6150 User Manual the core board. Users can connect the pin headers on the core board and connect the download and core JTAG ports with DuPont cable. To achieve core board program download and debug of the FPGA chip without the carrier board.
  • Page 16 FPGA Video Processing Development Platform AV6150 User Manual In addition, the normal operation of DDR3 requires DDR3 address line and control line to provide termination voltage VTT and DDR3 chip reference voltage VREF, VTT and VREF voltage are both 0.75V, the following Figure 3-3-2 is the power part schematic.

  • Page 17: Part 3.4: Spi Flash

    FPGA Video Processing Development Platform AV6150 User Manual DDR3 is connected to the BANK3 of the FPGA. DDR3 Pin Assignment Pin Name FPGA Pin Pin Name FPGA Pin DDR3_A[0] DDR3_A[11] DDR3_A[1] DDR3_A[12] DDR3_A[2] DDR3_A[13] DDR3_A[3] DDR3_A[14] DDR3_A[4] DDR3_BA[0] DDR3_A[5] DDR3_BA[1]...
  • Page 18 FPGA Video Processing Development Platform AV6150 User Manual Due to the non-volatile nature of SPI FLASH, it can be used as a boot device for the system to store the boot image of the system. These images mainly include FPGA bit files, core application code and other user data files. The specific models and related parameters of SPI FLASH are shown in Table 3-4-1.

  • Page 19: Part 3.5: Crystal Oscillator On Core Board

    FPGA Video Processing Development Platform AV6150 User Manual SPI Flash pin assignments: Pin Name FPGA Pin SPI_CLK SPI_CSn AB20 SPI_DIN AA20 SPI_DOUT Part 3.5: Crystal oscillator on Core Board The core board carries a 50M active crystal oscillator and a 27M active crystal oscillator.

  • Page 20: Part 3.6: Led Light On Core Board

    FPGA Video Processing Development Platform AV6150 User Manual Figure 3-5-2: Crystal oscillator on the Core Board Crystal oscillator Pin Assignment Input Clock FPGA Pin AB13 50MHz 27MHz Part 3.6: LED Light on Core Board There are 6 red LED lights on the AC6045 FPGA core board, one of which is the power indicator light (PWR), one is the configuration LED light (DONE), and four are the user LED light.
  • Page 21 FPGA Video Processing Development Platform AV6150 User Manual Figure 3-6-2: Power Indicator and Configure Indicator on the Core Board The schematic diagram of the four user LED sections is shown below. In Figure 3-6-3, When the FPGA pin output is logic 0, the LED will be lit.

  • Page 22: Part 3.7: Av6150 Power Supply

    FPGA Video Processing Development Platform AV6150 User Manual User LEDs Pin Assignment LED Name FPGA Pin LED0 LED1 LED2 LED3 Part 3.7: AV6150 Power Supply In order for FGPA to work properly, it is necessary to provide three power supplies for P3V3, P1V2 and VCCIO for the FPGA. P3V3 is for the VCCAUX of the FPGA, the voltage is 3.3V;...
  • Page 23 FPGA Video Processing Development Platform AV6150 User Manual Figure 3-7-1：Power Supply on core board schematic 23 / 55 Contact Email: rachel.zhou@alinx.com.cn...

  • Page 24: Part 3.8: Powe Interface On Core Board

    FPGA Video Processing Development Platform AV6150 User Manual Figure 3-7-2: Power Supply Circuit on the AC6150 FPGA Core Board Part 3.8: Powe interface on Core Board In order to make the core board work normally, the FPGA expansion baord needs to provide a +5V power supply to the core board through the expansion ports.

  • Page 25: Part 3.9: Expansion Ports

    FPGA Video Processing Development Platform AV6150 User Manual If you need to debug the core board separately, power the core board through the Mini USB port (J2) of the core board, the Mini USB cable is connected to the USB port of the computer.
  • Page 26 FPGA Video Processing Development Platform AV6150 User Manual Figure 3-9-1: Expansion Ports P1 26 / 55 Contact Email: rachel.zhou@alinx.com.cn...
  • Page 27 FPGA Video Processing Development Platform AV6150 User Manual Figure 3-9-2: Expansion Ports P2 27 / 55 Contact Email: rachel.zhou@alinx.com.cn...
  • Page 28 FPGA Video Processing Development Platform AV6150 User Manual Figure 3-9-3: Expansion Ports P1&P2 on the Core Board 28 / 55 Contact Email: rachel.zhou@alinx.com.cn...

  • Page 29: Part 3.10: Structure Diagram

    FPGA Video Processing Development Platform AV6150 User Manual Part 3.10: Structure Diagram Figure 3-10-1: AC6150 FPGA Core board (Top view) Figure 3-10-2: AC6150 FPGA Core board (Top view) 29 / 55 Contact Email: rachel.zhou@alinx.com.cn...

  • Page 30: Part 4: Carrier Board

    FPGA Video Processing Development Platform AV6150 User Manual Part 4: Carrier board Part 4.1: Carrier board Introduction Through the previous function introduction, you can understand the function of the carrier board part  4-channel Video Input TW2867  1-channel HDMI Input SiI9013 ...

  • Page 31: Part 4.2: Vga Display Interface

    FPGA Video Processing Development Platform AV6150 User Manual Basic experiment 1) DDR3 test experiment 2) VGA output color bar experiment 3) HDMI output color bar experiment 4) TW2867 input to VGA display experiment 5) I2C communication experiment 6) RGB to Ycbcr experiment...
  • Page 32 RGB digital signals to output VGA video signals, up to 1080p@60Hz output. In the AV6150 FPGA development board, the RGB digital signal output by the FPGA is 24-bit color, of which 8 colors are red, green and blue. In the schematic design, the 8-bit data of the red, green and blue output of the FPGA is connected to the 3-way DA of the ADV7123.

  • Page 33: Part 4.3: Hdmi Output Interface

    FPGA Video Processing Development Platform AV6150 User Manual VGA Signal Pin Assignment Pin Name FPGA Pin VGA_CLK VGA_EN VGA_HS VGA_VS VGA_R7 VGA_R6 VGA_R5 VGA_R4 VGA_R3 VGA_R2 VGA_R1 VGA_R0 VGA_G7 VGA_G6 VGA_G5 VGA_G4 VGA_G3 VGA_G2 VGA_G1 VGA_G0 VGA_B7 VGA_B6 VGA_B5 VGA_B4...
  • Page 34 FPGA Video Processing Development Platform AV6150 User Manual of Silion Image , which supports up to 1080P@60Hz output and supports 3D output. Among them, IIC interface of SIL9134 is connected with STM32F103, SIL9134 is initialized and controlled by STM32F103, and other pins of SIL9134 are connected to FPGA.

  • Page 35: Part 4.4: Hdmi Input Interface

    FPGA Video Processing Development Platform AV6150 User Manual HDMI Output Interface Pin Assignment Pin Name FPGA Pin 9134_CLK 9134_HS 9134_VS 9134_DE 9134_D[0] 9134_D[1] 9134_D[2] 9134_D[3] AB18 9134_D[4] AA18 9134_D[5] AB17 9134_D[6] AB14 9134_D[7] 9134_D[8] AA14 9134_D[9] 9134_D[10] 9134_D[11] 9134_D[12] AB19...
  • Page 36 FPGA Video Processing Development Platform AV6150 User Manual Image , which supports up to 1080P@60Hz input and Support data output in different formats. Among them, IIC interface of SIL9013 is connected with STM32F103, SIL9013 is initialized and controlled by STM32F103, and other pins of SIL9013 are connected to FPGA.

  • Page 37: Part 4.5: Video Input Interface

    FPGA Video Processing Development Platform AV6150 User Manual HDMI Input Interface Pin Assignment Pin Name FPGA Pin AA12 9013_CLK 9013_HS 9013_VS 9013_DE 9013_D[0] 9013_D[1] 9013_D[2] 9013_D[3] 9013_D[4] 9013_D[5] 9013_D[6] 9013_D[7] 9013_D[8] AA10 9013_D[9] AB12 9013_D[10] AB10 9013_D[11] 9013_D[12] 9013_D[13] AB15...
  • Page 38 FPGA Video Processing Development Platform AV6150 User Manual PAL/NTSC/SECAM automatic identification, output BT656, multiplexable bus, FPGA-side demultiplexing, save IO Among them, the IIC interface and reset pin of TW2867 are connected to STM32F103, and the TW2867 is initialized and controlled by STM32F103.

  • Page 39: Part 4.6: Gigabit Ethernet Interface

    FPGA Video Processing Development Platform AV6150 User Manual Figure 4-5-2: Video Input Interface on the carrier board Video Input Interface Pin Assignment Pin Name FPGA Pin 2867_CLKP 2867_CLKN 2867_D[0] 2867_D[1] 2867_D[2] 2867_D[3] 2867_D[4] 2867_D[5] 2867_D[6] 2867_D[7] Part 4.6: Gigabit Ethernet Interface...
  • Page 40 FPGA Video Processing Development Platform AV6150 User Manual The RTL8211EG chip supports 10/100/1000 Mbps network transmission rate and communicates with the FPGA through the GMII interface. RTL8211EG supports MDI/MDX adaptive, various speed adaptations, Master/Slave adaptation, and support for MDIO bus for PHY register management.
  • Page 41 FPGA Video Processing Development Platform AV6150 User Manual Figure 4-6-1: Gigabit Ethernet Interface Schematic Figure 4-6-2: Gigabit Ethernet interface on the Carrier board 41 / 55 Contact Email: rachel.zhou@alinx.com.cn...

  • Page 42: Part 4.7: Arm Controller

    FPGA Video Processing Development Platform AV6150 User Manual Gigabit Ethernet pin assignments： Pin Name FPGA Pin Description RGMII transmit clock E_GCLK Transmit Data bit0 E_TXD0 Transmit Data bit1 E_TXD1 Transmit Data bit2 E_TXD2 Transmit Data bit3 E_TXD3 Transmit enable signal...
  • Page 43 FPGA Video Processing Development Platform AV6150 User Manual Figure 4-7-1: ARM STM32F103 Schematic Figure 4-7-2: STM32F103 on the FPGA carrier board 43 / 55 Contact Email: rachel.zhou@alinx.com.cn...
  • Page 44 FPGA Video Processing Development Platform AV6150 User Manual At the same time, the ARM chip also brings out real-time clock, EEPROM, 4 LEDs, and serial ports. Part 4.7.1: Real Time Clock Figure 4-7-3: RTC Schematic Figure 4-7-4: RTC on the carrier board 44 / 55 Contact Email: rachel.zhou@alinx.com.cn...
  • Page 45 FPGA Video Processing Development Platform AV6150 User Manual ARM corresponding pin: Pin Name ARM Pin RTC_SCLK RTC_IO RTC_RESET Part 4.7.2: EEPROM Figure 4-7-5: EEPROM Schematic Figure 4-7-6: EEPROM on the carrier board ARM corresponding pin: Pin Name ARM Pin 24LC04_SDA...
  • Page 46 FPGA Video Processing Development Platform AV6150 User Manual Part 4.7.3: LED Figure 4-7-7: LED Schematic Figure 4-7-8: LED on the carrier board ARM corresponding pin: Pin Name ARM Pin LED0 LED1 LED2 LED3 46 / 55 Contact Email: rachel.zhou@alinx.com.cn...
  • Page 47 FPGA Video Processing Development Platform AV6150 User Manual Part 4.7.4: USB to Serial Port Figure 4-7-9: USB to Serial Port Schematic Figure 4-7-10: USB to Serial Port on the expansion port ARM corresponding pin: Pin Name ARM Pin RXD1 TXD1 47 / 55 Contact Email: rachel.zhou@alinx.com.cn...
  • Page 48 FPGA Video Processing Development Platform AV6150 User Manual Part 4.7.5: SD Card Slot ARM communicates with the Micro SD card through the SPI interface for reading and storing SD card data. Figure 4-7-11: Mini SD Schematic Figure 4-7-12: SD Card Slot on the carrier board...

  • Page 49: Part 4.8: Camera Module Interface

    FPGA Video Processing Development Platform AV6150 User Manual Part 4.8: Camera Module Interface The development board includes an 18-pin CMOS camera interface that can be connected to the OV7670 camera module and the OV5640 camera module for video capture. After acquisition, the monitor can be connected via HDMI or VGA interface for display.

  • Page 50: Part 4.9: Expansion Header

    Part 4.9: Expansion Header The carrier board is reserved with one 0.1inch spacing standard 40-pin expansion header J13 which is used to connect the ALINX modules or the external circuit designed by the user. The expansion port has 40 signals, of which 1-channel 5V power supply, 2-channel 3.3 V power supply, 3-channle...
  • Page 51 FPGA Video Processing Development Platform AV6150 User Manual Figure 4-9-1: Expansion header J13 schematic Figure 4-9-2: Expansion header J13 on the Carrier board J13 Expansion Header Pin Assignment Pin Number FPGA Pin Pin Number FPGA Pin 51 / 55 Contact Email: rachel.zhou@alinx.com.cn...
  • Page 52 FPGA Video Processing Development Platform AV6150 User Manual D3V3 D3V3 Part 4.10: JTAG Interface A JTAG interface is reserved on the FPGA carrier boardfor downloading FPGA programs or firmware to FLASH. In order to prevent damage to the FPGA chip caused by hot plugging, a protection diode is added to the JTAG signal to ensure that the voltage of the signal is within the range accepted by the FPGA to avoid damage of the FPGA chip.
  • Page 53 FPGA Video Processing Development Platform AV6150 User Manual Figure 4-10-2: JTAG Interface on the carrier board Be careful not to hot swap when JTAG cable is plugged and unplugged. Part 4.11: Buttons The FPGA carrier board contains two user buttons KEY1~KEY2. All buttons are connected to the normal IO of the FPGA.
  • Page 54 FPGA Video Processing Development Platform AV6150 User Manual Figure 4-11-2: User Buttons on the Carrier board Buttons Pin Assignment Net Name FPGA PIN KEY1 KEY2 Part 4.12: Power Supply The power input voltage of the FPGA development board is DC5V. It is converted into D3V3, D1V2, D1V8 three-way power supply through three-way DC/DC power chip MP1482.
  • Page 55 FPGA Video Processing Development Platform AV6150 User Manual Figure 4-12-1 Power Design Schematic on the carrier board Figure 4-12-2: Power Supply circuit on the carrier board 55 / 55 Contact Email: rachel.zhou@alinx.com.cn...

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