Flexible Swj-Dp Pin Assignment; Internal Pull-Up And Pull-Down Resistors On Jtag Pins; Table 8. Debug Port Pin Assignment; Table 9. Swj I/O Pin Availability - ST STM32F4 Series Getting Started

AN4488
SWJ-DP pin name
JTMS/SWDIO
JTCK/SWCLK
JTDI
JTDO/TRACESWO
JNTRST
6.3.2

Flexible SWJ-DP pin assignment

After reset (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned as
dedicated pins immediately usable by the debugger host (note that the trace outputs are not
assigned except if explicitly programmed by the debugger host).
However, some of the JTAG pins shown in
function through the GPIOx_AFRx registers.
Full SWJ (JTAG-DP + SW-DP) - reset state
Full SWJ (JTAG-DP + SW-DP) but without
JNTRST
JTAG-DP disabled and SW-DP enabled
JTAG-DP disabled and SW-DP disabled
Table 9 shows the different possibilities to release some pins.
For more details, see the reference manual
website www.st.com.
6.3.3

Internal pull-up and pull-down resistors on JTAG pins

The JTAG input pins must not be floating since they are directly connected to flip-flops to
control the debug mode features. Special care must be taken with the SWCLK/TCK pin that
is directly connected to the clock of some of these flip-flops.

Table 8. Debug port pin assignment

JTAG debug port
Type Description
JTAG test mode
I
selection
I JTAG test clock
I JTAG test data input
O JTAG test data output
I JTAG test nReset

Table 9. SWJ I/O pin availability

Available Debug ports
DocID026304 Rev 3
SW debug port
Type Debug assignment
Serial wire data
I/O
input/output
I Serial wire clock
- -
TRACESWO if async
-
trace is enabled
- -
Table 9 can be configured to an alternate
SWJ I/O pin assigned
PA13 / PA14 /
JTMS/ JTCK/
SWDIO SWCLK
X X
X X
X X
Released
(Table 1), available from the STMicroelectronics
Debug management
Pin
assignmen
t
PA13
PA14
PA15
PB3
PB4
PA15 / PB3 / PB4/
JTDI JTDO JNTRST
X X X
X X
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