Flexible Swj-Dp Pin Assignment; Table 5. Swj Debug Port Pins; Table 6. Flexible Swj-Dp Assignment - ST STM32H7 3 Series Application Note

Debug management
SWJ-DP pin name
JTMS/SWDIO
JTCK/SWCLK
JTDI
JTDO/TRACESWO
NJTRST
5.3.2

Flexible SWJ-DP pin assignment

After RESET (SYSRESETn or PORESETn), all the five pins used for the SWJ-DP are
assigned as dedicated pins immediately usable by the debugger host (note that the trace
outputs are not assigned except if explicitly programmed by the debugger host).
However, the STM32H743/753xx devices offer the possibility of disabling some or all of the
SWJ-DP ports and so, of releasing the associated pins for general-purpose IO (GPIO)
usage.
Table 6 shows the different possibilities to release some pins.
Available debug ports
Full SWJ (JTAG-DP + SW-DP) - reset state
Full SWJ (JTAG-DP + SW-DP) but without
NJTRST
JTAG-DP disabled and SW-DP enabled
JTAG-DP disabled and SW-DP disabled
For more details on how to disable SWJ-DP port pins, please refer to the reference manual
I/O pin alternate function multiplexer and mapping section.
28/48

Table 5. SWJ debug port pins

JTAG debug port
Type Description
JTAG test mode
I
Selection
I JTAG test clock
I JTAG test data input
JTAG test data
O
output
I JTAG test nReset

Table 6. Flexible SWJ-DP assignment

PA13/
JTMS/
SWDIO
X
X
X
DocID029918 Rev 1
SW debug port
Type Debug assignment
Serial wire data
IO
input/output
I Serial wire clock
-
TRACESWO if
- asynchronous trace is
enabled
-
SWJ IO pin assigned
PA14/JTCK
PA15/JTDI
/SWCLK
X X
X X
X
Released
AN4938
Pin
assignment
PA13
PA14
- PA15
PB3
- PB4
PB3/JTDO PB4/NJTRST
X X
X
-
-