Regulator On/Off And Internal Reset On/Off Availability; Table 3. Regulator On/Off And Internal Power Supply Supervisor Availability - ST STM32F4 Series Getting Started

AN4488
The following conditions must be respected:
•
V
DD
domains.
•
If the time for V
reach 1.7 V, then PA0 should be kept low to cover both conditions: until V
V12 minimum value and until V
•
Otherwise, if the time for V
V
DD
•
If V
CAP
be asserted low externally.
2.3.7

Regulator ON/OFF and internal reset ON/OFF availability

Table 3. Regulator ON/OFF and internal power supply supervisor availability

Package pins
48
64
100
Packages with
pins on 4 edges
144
176
208
100
144
BGA Packages 169
176
216
49
81
Chip Scale
Packages
90
143
1. BYPASS_REG internally connected to V
2. PDR_ON internally connected to V
3. PDR_ON can be permanently set to VSS for STM32F411xx and STM32F446xx devices. For other devices, see Chapter
2.3.4
4. BYPASS_REG set to V
5. BYPASS_REG set to V
should always be higher than V
to reach V12 minimum value is smaller than the time for V
CAP
to reach 1.7 V, then PA0 could be asserted low externally.
goes below V12 minimum value and V
Regulator ON
(1)
Yes
(4)
Yes
(1)
Yes
(4)
Yes
(1)
Yes
(4)
Yes
SS
DD
SS
DD
DocID026304 Rev 3
to avoid current injection between power
CAP
reaches 1.7 V.
DD
to reach V12 minimum value is smaller than the time for
CAP
DD
Regulator OFF
No
(5)
Yes
No
(5)
Yes
PDR_ON set to V
No
(5)
Yes
Power supplies
is higher than 1.7 V, then PA0 must
Power supply Power supply
supervisor ON supervisor OFF
(2)
Yes
Yes
PDR_ON external
DD
to
DD
reaches
CAP
No
Yes
(3)
control
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