Reference Design; Description; Clock; Reset - ST STM32F4 Series Getting Started

AN4488
8

Reference design

8.1

Description

The reference design shown in
integrated microcontroller running at 168 MHz, that combines the Cortex
CPU core with 1 Mbyte of embedded Flash memory and 192+4 Kbytes of SRAM including
64-Kbytes of CCM (core coupled memory) data RAM
This reference design is intended to work with a V
VDD_MCU) and using embedded voltage regulator for 1.2V core supplies (BYPASS_REG =
GND), although BYPASS_REG = VDD_MCU is possible with JP1 jumper change, the
additional hardware as described in
This reference design can be tailored to any other device listed in
package, using the pins correspondence given in
packages.
8.1.1

Clock

Two clock sources are used for the microcontroller:
•
LSE: X2– 32.768 kHz crystal for the embedded RTC
•
HSE: X1– 25 MHz crystal for the STM32F4xxxx microcontroller
Refer to
8.1.2

Reset

The reset signal in
•
Reset button (B1)
• Debugging tools via the connector CN1
Refer to
8.1.3

Boot mode

The boot option is configured by setting switches SW2 (Boot 0) and SW1 (Boot 1). Refer to
Section 5: Boot configuration on page
Note: In low-power mode (more specially in Standby mode) the boot mode is mandatory to be
able to connect to tools (the device should boot from the SRAM).
8.1.4

SWJ interface

The reference design shows the connection between the STM32F4xxxx and a standard
JTAG connector. Refer to
Note: It is recommended to connect the reset pins so as to be able to reset the application from
the tools.
8.1.5

Power supply

Refer to
Section 4: Clocks on page
Figure 26 is active low. The reset sources include:
Section 2.3: Reset & power supply supervisor on page
Section 6: Debug management on page
Section 2: Power supplies on page
Figure 26, is based on the STM32F407IG(H6), a highly
DD
Section 2.3.6 is not present.
Table 12: Reference connection for all
26.
30.
7.
DocID026304 Rev 3
Reference design
®
-M4 32-bit RISC
.
from 1.8V minimum (PDR_ON =
Table 1 with different
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32.
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