CMOSTEK CMT2380F17 Manual page 71

Bit 2~0: SCKS2 ~ SCKS0, programmable System Clock Selection.
CKCON2: Clock Control Register 2
SFR Page = P Only
SFR Address = 0x40
Bit 7
Name --
R/W W
Reset V alue
0
Bit 4: IHRCOE, Internal High frequency RC Oscillator Enable.
0: Disable internal high frequency RC oscillator.
1: Enable internal high frequency RC oscillator. If this bit is set by CPU software, it needs 32 us to have
stable output after IHRCOE is enabled.。
Bit 3~2：MCKS[1:0], MCK clock source selection.
MCKS[1:0] MCK Source Selection
00
01
10
11
Note: It needs to set ENCKM = 1 to enable CKM.
Note: Needs to be careful of the limitation of CPUCLK and SYSCLK. Needs to use SCKS[2:0] and CCKS
to choose proper range of CPUCLK and SYSCLK to not exceed the limitation. CPUCLK
≤
50MHz.
Bit 1~0: OSCS[1:0], OSCin Source selection.
OSCS[1:0]
00
01
10
11
CKCON3: Clock Control Register 3
SFR Page = P only
SFR Address = 0x41
Bit
7
Name WDTCS[1:0]
R/W R/W
Reset V alue 0
Bit 7~6: WDT clock source selection.
SCKS[2:0]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
6 5
-- --
W W
0 0
CKMS0 = 0
OSCin
CKMI x4 / x6
CKMI x5.33 / x8
CKMI x8 / x12
ECKI, external clock input (P6.0) as OSCin
6 5
FWKP
R/W R/W
0 0
System Clock (SYSCLK)
MCKDO/1
MCKDO/2
MCKDO/4
MCKDO/8
MCKDO/16
MCKDO/32
MCKDO/64
MCKDO/128
4 3
IHRCOE MCKS[1:0]
R/W R/W
1 0
OSCin =12MHz
CKMIS = [01]
CKMS0 = 1
12MHz
24MHz 36MHz
32MHz 48MHz
48MHz 72MHz
OSCin source Selection
IHRCO
ILRCO
Reserved
4 3
WDTFS MCKD[1:0]
R/W R/W
0 0
Rev0.1 | 71/347
CMT2380F17
2 1
OSCS[1:0]
R/W R/W
0 0
OSCin =11.059MHz
CKMIS = [01]
CKMS0 = 0 CKMS0 = 1
11.059MHz
22.118MHz 33.177MHz
29.491MHz 44.236MHz
44.236MHz 66.354MHz
≤
36MHz, SYSCLK
2 1
--
R/W W
0 0
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0
R/W
0
0
--
W
0