CMOSTEK CMT2380F17 Manual page 237

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S1M0X3 also controls the SPI transfer speed. If S1M0X3 = 1, the SPI clock frequency is SYSCLK/4.
Otherwise, the SPI clock frequency is SYSCLK/12.
The SPI master in MG82F6D17 uses the TXD1 as SPICLK, RXD1 as MOSI, and S1MI as MISO. nSS is
selected by MCU software on other port pin. Figure 19–2 shows the SPI connection. It also can support the
configuration for multiple slaves communication in Figure 19–3.
Figure 19–2. Serial Port 1 Mode 4, Single Master and Single Slave configuration (n = 1)
Figure 19–3. Serial Port 1 Mode 4, Single Master and Multiple Slaves configuration (n = 1)
The SPI master satisfies the transfer with the full function SPI module of Megawin MG82/84 series MCU
with CPOL, CPHA and DORD selection. For CPOL and CPHA condition, MG82F6D17 uses an easy way by
initialize SPI clock polarity to fit them. Table 18–12 shows the serial port Mode 4 mapping with the four SPI
operating mode.
Table 19–12. SPI mode mapping with Serial Port Mode 4 configuration
SPI Mode
0 1 1
1 0 2
1 1 3
0 0 4
0 1 5
1 0 6
1 1 7
CPOL CPHA Configuration in TXD1
Rev0.1 | 237/347
8-bit UART variable
9-bit UART SYSCLK/64, /32 or /192, /96
9-bit UART variable
SPI Master SYSCLK/12 or SYSCLK/4
Reserved variable
Reserved Reserved
Reserved variable
CMT2380F17
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