Timer 2 Register - CMOSTEK CMT2380F17 Manual

How to Program Split Timer 2 in Clock-out Mode
•
Select TL2 clock source.
•
Determine the 8-bit reload value from the formula and enter it in the RCAP2L register. Enter the
same reload value as the initial value in the TL2 register.
•
Set T2OE bit in T2MOD register.
•
Set TR2L bit in T2CON register to start the Timer 2.
In the Clock-Out mode, TL2 rollovers will also generate an interrupt, TF2L. This is similar to when TL2 is
used as a baud-rate generator. It is possible to use TL2 as a baud rate generator and a clock generator
simultaneously. Note, however, that the baud-rate and the clock-out frequency depend on the same overflow
rate of TL2 in split Timer 2. The TF2L interrupt is enabled by TL2IE in T2CON register.

16.2.12 Timer 2 Register


T2CON：Timer 2 Control Register
SFR Page = 0 Only
SFR Address = 0xC8
Bit 7
Name TF2
R/W R/W
Reset V alue
0
Bit 7: TF2, Timer 2 overflow flag.
0: TF2 must be cleared by software.
1: TF2 is set by a Timer 2 overflow happens. TF2 will not be set when either RCLK=1 or TCLK=1.
Bit 6: EXF2, Timer 2 external flag.
0: EXF2 must be cleared by software.
1: Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX
pin and EXEN2=1 or a positive transition on T2EX and T2EXH=1. When Timer 2 interrupt is enabled,
EXF2=1 will cause the CPU to vector to the Timer 2 interrupt routine.
TL2IS (T2MOD1.5) must be cleared to enable access to the RCLK bit.
Bit 5: RCLK, Receive clock flag.
0: Causes Timer 1 overflow to be used for the receive clock.
1: Causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3.
TL2IS (T2MOD1.5) must be set to enable access to the TF2L bit.
Bit 5: TF2L, TL2 overflow flag in Timer 2 split mode.
0: TF2L must be cleared by software.
1: TF2L is set by TL2 overflow happened in Timer 2 split mode.
Figure 15-26. Split Timer 2 in Clock-Out Mode
6 5
RCLK/
EXF2
TF2L
R/W R/W
0 0
Rev0.1 | 153/347
4 3
TCLK/
EXEN2
TL2IE
R/W R/W
0 0
CMT2380F17
2 1
TR2 C/T2
R/W R/W
0 0
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0
CP/RL2
R/W
0