CMOSTEK CMT2380F17 Manual page 290


ADCFG0：ADC Configuration Register 0
SFR Page = 0 Only
SFR Address = 0xC3
7
Bit
Name
R/W
R/W
0
Reset V alue
Bit 7~5: ADC Conversion Clock Select bits.
Note:
1. SYSCLK is the system clock.
2. S0TOF is UART0 Baud-Rate Generator Overflow.
3. T2OF is Timer2 Overflow.
Bit 4: ADRJ, ADC result Right-Justified selection.
0: The most significant 8 bits of conversion result are saved in ADCDH [7:0], while the least significant 2
bits in ADCDL[7:6].
1: The most significant 2 bits of conversion result are saved in ADCDH [1:0], while the least significant 8
bits in ADCDL[7:0].
(1) If ADRJ = 0

ADCDH：ADC Date High Byte Register
SFR Page = 0~F
SFR Address = 0xC6
Bit 7
Name
R/W
R
Reset V alue X
6 5
ADCKS[2:0]
R/W R/W
0 0
ADCKS[2:0]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
6 5
R R
X X
4 3
ADRJ ACHS
R/W R/W
0 X
ADC Clock Selection
SYSCLK
SYSCLK/2
SYSCLK/4
SYSCLK/8
SYSCLK/16
SYSCLK/32
S0TOF/2
T2OF/2
4 3
ADCD[11:4]
R R
X X
Rev0.1 | 290/347
CMT2380F17
2 1
SMPF ADTM1
R/W R/W
X 0
2 1
R R
X X
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0
ADTM0
R/W
0
0
R
X