CMOSTEK CMT2380F17 Manual page 291


ADCL： ADC Data Low Byte Register
SFR Page = 0~F
SFR Address = 0xC5
7
Bit
Name
R
R/W
X
Reset V alue
(2) If ADRJ = 1

ADCDH
7
Bit
--
Name
R
R/W
X
Reset V alue

ADCDL
7
Bit
Name
R
R/W
X
Reset V alue
When in Single-ended Mode, conversion codes are represented as 12-bit unsigned integers. Inputs are
measured from '0' to VDD(VREF) x 4095/4096. Example codes are shown below for both right-justified and
left-justified data. Unused bits in the ADCDH and ADCDL registers are set to '0'.
Input Voltage (Single-Ended)
VDD x 4095/4096
VDD x 2048/4096
VDD x 1023/4096
VDD x 512/4096
VDD x 256/4096
VDD x 128/4096
Bit 3: ACHS, ADC Auxiliary CHannel Select. Decode ACHS and CHS3~0 to select ADC input channel. Bit
2: SMPF. ADC channel sample & hold flag.
0: The flag must be cleared by software.
1: This flag is set when an ADC channel sample & hold is completed. An interrupt is invoked if it is
enabled. The interrupt on this flag can be enabled by SMPFIE (ADCFG1.5).
Bit 1~0: ADC Trigger Mode selection.
ADTM[1:0]

ADCFG1：ADC Configuration Register 1
SFR Page = 1 Only
SFR Address = 0xC3
Bit 7
Name IGADCI
6 5
ADCD[3:0]
R R
X X
6 5
-- --
R R
X X
6 5
R R
X X
0
ADC Conversion Start Selection
0 0
0 1
1 0
1 1
6 5
EADCWI SMPFIE
Rev0.1 | 291/347
4 3
--
R R
X X
4 3
--
R R
X X
4 3
ADCD[7:0]
R R
X X
ADCDH:ADCDL
（ADRJ = 0）
0xFFF0
0x8000
0x4000
0x2000
0x1000
0x0800
0x0000
Set ADCS
Timer 0 overflow
Free running mode
S0 BRG overflow
4 3
SIGN AOS.3
CMT2380F17
2 1
-- --
R R
X X
2 1
ADCD[11:8]
R R
X X
2 1
R R
X X
ADCDH:ADCDL
（ADRJ = 1）
0x0FFF
0x0800
0x0400
0x0200
0x0100
0x0080
0x0000
2 1
AOS.2 AOS.1
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0
--
R
X
0
R
X
0
R
X
0
AOS.0