CMOSTEK CMT2380F17 Manual page 255

Bit 3: CPOL, SPI clock polarity select
0: SPICLK is low when Idle. The leading edge of SPICLK is the rising edge and the trailing edge is the
falling edge. 1: SPICLK is high when Idle. The leading edge of SPICLK is the falling edge and the trailing
edge is the rising edge.
Bit 2: CPHA, SPI clock phase select
0: Data is driven when /SS pin is low (SSIG=0) and changes on the trailing edge of SPICLK. Data is
sampled on the leading edge of SPICLK.
1: Data is driven on the leading edge of SPICLK, and is sampled on the trailing edge. (Note: If SSIG=1,
CPHA must not be 1, otherwise the operation is not defined.)
Bit 1~0: SPR1-SPR0, SPI clock rate select 0 & 1 (associated with SPR2, when in master mode)
SPR2 SPR1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Note:

SYSCLK is the system clock.

S0TOF is UART0 Baud-Rate Generator Overflow.

T0OF is Timer 0 Overflow.
SPI Clock
SPR0
Selection
0 SYSCLK/4
1 SYSCLK/8
0 SYSCLK/16
1 SYSCLK/32
0 SYSCLK/64
1 SYSCLK/2
0 S0TOF/6
1 T0OF/6
SPI Clock Rate @
SYSCLK=12MHz
3 MHz
1.5 MHz
750 KHz
375 KHz
187.5 KHz
6 MHz
Variable
Variable
Rev0.1 | 255/347
CMT2380F17
SPI Clock Rate @
SYSCLK=48MHz
12 MHz
6 MHz
3 MHz
1.5 MHz
750 KHz
24 MHz
Variable
Variable
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