CMOSTEK CMT2380F17 Manual page 313

0 0
0 1 CKMI x4/x6
1 0 CKMI x5.33/x8
1 1 CKMI x8/x12
Note: It needs to set ENCKM = 1 to enable CKM.
Note: Needs to be careful of the limitation of CPUCLK and SYSCLK. Needs to use SCKS[2:0] and CCKS
to choose proper range of CPUCLK and SYSCLK to not exceed the limitation. CPUCLK
≤
SYSCLK 50MHz.
Bit 1~0: OSCS[1:0], OSCin Source selection.

CKCON3：Clock Control Register 3
SFR Page = P
SFR Address = 0x41
7
Bit
WDTCS1
Name
R/W
R/W
0
Reset V alue
Bit 7~6: WDTCS1~0, WDT Clock Source selection [1:0].
Bit 5: FWKP, MCU Fast wake up control.
0: Select MCU for normal wakeup time about 120us from power-down mode. 1: Select MCU for fast
wakeup time about 30us from power-down mode.
Bit 4: WDTFS. WDT overflow source selection.
0: Select WDT bit-8 overflow as WDT event source. 1: Select WDT bit-0 overflow as WDT event source.
Bit 3~2: MCKD[1:0], MCK Divider Output selection.
MCKD[1:0]
0 0
0 1
1 0
1 1
Bit 1~0: Reserved. In case of writting CKCON3, these two bits must be written to0" by software.

CKCON4：Clock Control Register 4
SFR Page = P only
SFR Address = 0x42
7
Bit
OSCin
24MHz
32MHz
48MHz
OSCS[1:0]
0 0
0 1
1 0
1 1
6 5
WDTCS0 FWKP
R/W R/W
0 0
WDTCS1~0
00
01
10
11
MCKDO Frequency
MCKDO = MCK
MCKDO = MCK/2
MCKDO = MCK/4
MCKDO = MCK/8
6 5
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12MHz
36MHz 22.118MHz
48MHz 29.491MHz
72MHz 44.236MHz
OSCin source Selection
IHRCO
ECKI
ILRCO
Reserved
4 3
WDTFS MCKD1
R/W R/W
0 0
WDT 时钟源
ILRCO
ECKI
SYSCLK/12
S0TOF
if MCK = 12MHz
MCKDO = 12MHz
MCKDO = 6MHz
MCKDO = 3MHz
MCKDO = 1.5MHz
4 3
CMT2380F17
11.059MHz
33.177MHz
44.236MHz
66.354MHz
≤
2 1
MCKD0 --
R/W W
0 1
if MCK = 48MHz
MCKDO = 48MHz
MCKDO = 24MHz
MCKDO = 12MHz
MCKDO = 6MHz
2 1
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36MHz,
0
--
R/W
0
0