CMOSTEK CMT2380F17 Manual page 128

Bit 1: BOF0IE, Enable BOF0 (PCON1.1) Interrupt.
0: Disable BOF0 interrupt.
1: Enable BOF0 interrupt.
Bit 0: WDTFIE, Enable WDTF (PCON1.0) Interrupt.
0: Disable WDTF interrupt.
1: Enable WDTF interrupt.

PCON1：Power Control Register 1
SFR Page = 0~F & P
SFR Address = 0x97
Bit 7
Name SWRF
R/W
R/W
Reset V alue 0
Bit 7: SWRF, Software Reset Flag.
0: This bit must be cleared by software writing "1" to it.
1: This bit is set by hardware if a Software Reset occurs.
Bit 6: EXRF, External Reset Flag.
0: This bit must be cleared by software writing "1" to it.
1: This bit is set by hardware if an External Reset occurs.
Bit 4: RTCF, RTC overflow flag.
0: This bit must be cleared by software writing "1" on it. Software writing "0" is no operation.
1: This bit is only set by hardware when RTCCT overflows. Writing "1" on this bit will clear RTCF.
Bit 3: Reserved. Software must write "0" on this bit when PCON1 is written.
Bit 2: BOF1, Brown-Out Detection flag 1.
0: This bit must be cleared by software writing "1" to it.
1: This bit is set by hardware if the operating voltage matches the detection level of Brown-Out Detector 1
(4.2V/3.7/2.4/2.0).
Bit 1: BOF0, Brown-Out Detection flag 0.
0: This bit must be cleared by software writing "1" to it.
1: This bit is set by hardware if the operating voltage matches the detection level of Brown-Out Detector 0
(1.7V).
Bit 0: WDTF, WDT overflow flag.
0: This bit must be cleared by software writing "1" to it. 1: This bit is set by hardware if a WDT overflow
occurs.

AUXR2: Auxiliary Register 2
SFR Page = 0 only
SFR Address = 0xA3
Bit
7
Name STAF
R/W R/W
Reset V alue 0
Bit 7: STAF, Start Flag detection of STWI (SID).
0: Clear by firmware by writing "0" on it. STAF might be held within MCU reset period, so needs to
clear STAF in firmware initial.
1: Set by hardware to indicate the START condition occurred on STWI bus.
6 5
EXRF --
R/W W
0 0
6 5
STOF --
R/W W
0 0
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4 3
RTCF --
R/W W
0 0
4 3
-- T1X12
W R/W
0 0
CMT2380F17
2 1
BOF1 BOF0
R/W R/W
0 0
2 1
T0X12 T1CKOE
R/W R/W
0 0
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0
WDTF
R/W
0
0
T0CKOE
R/W
0