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CMT2380F17
CMOSTEK CMT2380F17 Manuals
Manuals and User Guides for CMOSTEK CMT2380F17. We have
1
CMOSTEK CMT2380F17 manual available for free PDF download: Manual
CMOSTEK CMT2380F17 Manual (347 pages)
Ultra Low Power Sub-1GHz Wireless MCU
Brand:
CMOSTEK
| Category:
Transceiver
| Size: 11 MB
Table of Contents
MCU Features
1
RF Features
1
System Features
1
Application
1
Description
2
Table of Contents
4
Electrical Specifications
11
Recommended Operating Conditions
11
Absolute Maximum Ratings
11
RF Power Consumption
12
Receiver
12
Transmitter
14
RF Operating Mode Switching Time
15
RF Frequency Synthesizer
15
Requirement on Crystals for RF Section
17
Controller DC Specification
17
Controller Power Consumption Characteristics
18
BOD Characteristics
18
Controller IHRCO Characteristics
18
Controller ILRCO Characteristics
19
Controller CKM Characteristics
19
Controller Flash Characteristics
19
Controller ADC Characteristics
19
IVR Characteristics
20
Controller Serial Port Timing Characteristics
21
Controller SPI Timing Characteristics
21
Receive Current and Supply Voltage Correlation
23
Correlation Among Receive Current, Supply Voltage and Temperature
24
Receive Sensitivity and Supply Voltage Correlation
25
Receive Sensitivity and Temperature Correlation
25
Transmit Power and Supply Voltage Correlation
26
Phase Noise
27
Pin Description
28
Chip Structure
32
Sub-Ghz Transceiver
35
Transmitter
35
Receiver
35
Transceiver Power-On Reset (POR)
35
Transceiver Crystal Oscillator
36
Transceiver Built-In Low Frequency Oscillator (LPOSC)
36
Transceiver Built-In Low Battery Detection
37
Receiver Signal Strength Indication (RSSI)
37
Phase Jump Detector (PJD)
37
Receiver Clock Data Recovery (CDR)
38
Fast Manual Frequency Hopping
39
Transceiver Control Interface and Operating Mode
39
Transceiver SPI Interface Timing
39
Transceiver FIFO Interface Timing
40
Transceiver Operating Status, Timing, and Power Consumption
41
Transceiver GPIO Function and Interrupt Mapping
44
80C51 CPU Function Description
47
CPU Register
47
CPU Timing
48
CPU Addressing Mode
49
Direct Addressing (DIR)
49
Indirect Addressing (IND)
49
Register Instruction (REG)
49
Register-Specific Instruction
49
Immediate Constant (IMM)
49
Index Addressing
49
Memory Organization
50
On-Chip Program Flash
50
On-Chip Data RAM
51
On-Chip Expanded RAM (XRAM)
52
Off-Chip External Data Memory Access
52
Declaration Identifiers in a C51-Compiler
52
XRAM Access
54
MOVX on 16-Bit Address with Dual DPTR
54
MOVX on 8-Bit Address with XRPS
55
Direct Memory Access Controller (DMA)
57
DMA Structure
57
DMA Operation
58
DMA Transfer Types
58
DMA Transfer Mode
59
Transfer Count & Address Pointer
59
Start a DMA Transfer
60
Suspend or Stop DMA Transfer
60
DMA Interrupt
60
DMA Loop Mode
61
Error Handling in DMA
61
Data Copied to CRC16
61
Timer 5 & Timer 6
61
DMA Register
62
Timer5 Register
64
Timer 6 Register
66
System Clock
68
Clock Structure
68
Clock Source Switching
69
On-Chip CKM (PLL)
69
Wake-Up Clock from CKM
69
Clock Register
70
Watch Dog Timer (WDT)
74
WDT Structure
74
WDT During Idle
74
WDT Register
75
WDT Hardware Option
77
Real-Time-Clock (Rtc)/System-Timer
78
System Reset
82
Reset Source
82
Power-On Reset (POR)
82
Note: POF0 Must be Cleared by Software
83
External Reset
83
Software Reset
84
Brown-Out Reset
84
WDT Reset
85
Illegal Address Reset
85
Power Management
86
Brown-Out Detector
86
Power Saving Mode
86
Slow Mode
86
Sub-Clock Mode
87
RTC Mode
87
Watch Mode
87
Monitor Mode
87
Idle Mode
87
Power-Down Mode
88
Interrupt Recovery from Power-Down
89
Reset Recovery from Power-Down
89
KBI Wakeup Recovery from Power-Down
89
Power Control Register
89
Configurable I/O Ports
93
IO Structure
93
Port 3 Quasi-Bidirectional IO Structure
93
Port 3 Push-Pull Output Structure
94
Port 3 Input-Only (High Impedance Input) Structure
94
Port 3 Open-Drain Output Structure
94
General Analog Input Only Structure
95
General Open-Drain Output with Pull-Up Resistor Structure
95
General Open-Drain Output Structure
95
General Port Digital Input Configured
96
General Push-Pull Output Structure
96
Port Pin Output Driving Strength Selection
96
Port Pin Output Fast Driving Selection
96
I/O Port Register
96
Port 1 Register
97
Port 2 Register
98
Port 3 Register
99
Port 4 Register
100
Port 6 Register
101
Port Output Driving Strength Control Register
101
Port Output Fast Driving Control Register
103
Port Function Redirection
104
Interrupt
112
Interrupt Structure
112
Interrupt Source
114
Interrupt Enable
117
Interrupt Priority
117
Interrupt Process
118
Nintx Input Source Selection and Input Filter (X=0~2)
119
Interrupt Register
120
Timers/Counters
130
Timer 0 and Timer 1
130
Timer 0/1 Mode 0
130
Timer 0/1 Mode 1
132
Timer 0/1 Mode 2
133
Timer 0/1 Mode 3
134
Timer 0/1 Programmable Clock-Out
134
Timer 0/1 Register
136
Timer 2
141
Timer 2 Mode 0 (Auto-Reload and External Interrupt)
141
Timer 2 Mode 1 (Auto-Reload with External Interrupt)
142
Timer 2 Mode 2 (Capture)
143
Timer 2 Mode 3 (Capture with Auto-Zero)
144
Split Timer 2 Mode 0 (AR and Ex. INT)
145
Split Timer 2 Mode 1 (AR with Ex. INT)
146
Split Timer 2 Mode 2 (Capture)
147
Split Timer 2 Mode 3 (Capture with Auto-Zero)
148
Split Timer 2 Mode 4 (8-Bit PWM Mode)
149
Baud-Rate Generator Mode (BRG)
149
Timer 2 Programmable Clock Output
151
Timer 2 Register
153
Timer 3
157
Timer 3 Mode 0 (Auto-Reload and External Interrupt)
157
Timer 3 Mode 1 (Auto-Reload with External Interrupt)
157
Timer 3 Mode 2 (Capture)
158
Timer 3 Mode 3 (Capture and Auto-Zero)
159
Split Timer 3 Mode 0 (Auto-Reload and External Interrupt)
159
Split Timer 3 Mode 1 (Auto-Reload with External Interrupt)
160
Split Timer 3 Mode 2 (Capture)
162
Split Timer 3 Mode 3 (Capture with Auto-Zero)
163
Split Timer 3 Mode 4 (8-Bit PWM Mode)
164
Timer 3 Programmable Clock Output
164
Timer 3 Register
166
Timer Global Control
170
Global Enable for All Timer Run
170
Global Control for All Timer Reload
171
Global Control for All Timer Stop
172
Programmable Counter Array (PCA0)
173
PCA Overview
173
PCA Timer/Counter
173
Compare/Capture Modules
179
Operation Modes of the PCA
182
Capture Mode
183
Buffered Capture Mode
183
16-Bit Software Timer Mode (Compare Mode)
185
High Speed Output Mode (Compare Output Mode)
185
Buffered 8-Bit PWM Mode
185
Un-Buffered 10/12/16-Bit PWM Mode
186
Buffered 10/12/16-Bit PWM Mode
187
COPM Mode
188
Buffered COPM Mode
189
FIFO Data Mode
190
Enhanced PWM Control
190
PCA Module Output Control
194
Variable Resolution on Central Aligned PWM
198
Serial Port 0 (UART0)
200
Serial Port 0 Mode 0
201
Serial Port 0 Mode 1
202
Serial Port 0 Mode 2 and Mode 3
203
Frame Error Detection
204
Multiprocessor Communications
204
Automatic Address Recognition
204
Baud Rate Setting
206
Baud Rate Selection in S0
206
Baud Rate in Mode 0
206
Baud Rate in Mode 2
207
Baud Rate in Mode 1 & 3
207
Using Timer 1 as the Baud Rate Generator
208
Using Timer 2 as the Baud Rate Generator
215
Using S0 Baud Rate Timer as the Baud Rate Generator (S0BRG)
220
Using S1 Baud Rate Timer as the Baud Rate Generator
221
Serial Port 0 Mode 4 (SPI Master)
221
Serial Port 0 Register
223
Serial Port 0 Enhance Function
226
S0 Baud Rate Generator (S0BRG)
228
Independent Baud Rate Generator S0BRG for S0
228
S0 Enhanced Mode
229
S0 LIN Bus Register
229
S0 Acts as 8-Bit Timer Mode
230
S0 Acts as 16-Bit Timer Mode
230
S0BRG Programmable Clock Output
231
Serial Port 1 (UART1)
232
Serial Port 1 Baud Rate Generator (S1BRG)
232
S1BRG Configuration (S1TME=0)
232
Baud Rate in Mode 0
232
Baud Rate in Mode 2
233
Baud Rate in Mode 1 & 3
233
Serial Port 1 Mode 4 (SPI Master)
236
8-Bit Timer Mode on S1BRG
238
16-Bit Timer Mode on S1BRG
240
S1BRT Programmable Clock Output
240
How to Program 8-Bit S1BRG in Clock-Out Mode
241
S1 Baud Rate Generator for S0
242
Serial Port 1 Register
242
Serial Peripheral Interface (SPI)
247
Typical SPI Configurations
248
Single Master & Single Slave
248
Dual Device, Where Either Can be a Master or a Slave
248
Single Master & Multiple Slaves
248
Configuring the SPI
249
Additional Considerations for a Slave
250
Additional Considerations for a Master
250
Mode Change on Nss-Pin
250
Transmit Holding Register Full Flag
250
Write Collision
250
SPI Clock Rate Select
251
Data Mode
252
Daisy-Chain Connection
254
Configuring the Daisy-Chain
254
SPI Register
254
Two Wire Serial Interface (TWI0/ I2C0)
258
Operating Modes
258
Master Transmitter Mode
259
Master Receiver Mode
260
Slave Transmitter Mode
260
Slave Receiver Mode
261
Miscellaneous States
261
Using the TWI/ I2C
262
The Figure below Shows How to Read the Flow Charts
262
TWI0/ I2C0 Register
268
Serial Interface Detection (STWI/SI2C)
272
SID Structure
272
SID Register
272
Beeper
274
Keypad Interrupt (KBI)
276
KBI Structure
276
KBI Register
276
General Purpose Logic (GPL-CRC)
279
GPL-CRC Structure
279
GPL-BOREV Structure
280
GPL Register
280
12-Bit ADC
282
ADC Structure
282
ADC Operation
283
ADC Input Channels
283
ADC Internal Voltage Reference
283
Starting a Conversion
283
ADC Conversion Rate
284
ADC Interrupts
284
ADC Window Detect
285
ADC Channel Scan Mode
286
Transfer ADC Data by DMA
286
I/O Pins Used with ADC Function
287
Idle and Power-Down Mode
287
How to Improve ADC Accuracy
287
ADC Register
288
Internal Voltage Reference (IVR, 1.4V)
296
IVR (1.4V) Structure
296
IVR Register
296
How to Read IVR (1.4V) ADC Prestored Value
296
ISP and IAP
298
CMT2380F17 Flash Memory Configuration
298
CMT2380F17 Flash Access in ISP/IAP
298
ISP/IAP Flash Page Erase Mode
299
ISP/IAP Flash Byte Program Mode
301
ISP/IAP Flash Read Mode
303
ISP Operation
304
Hardware Approached ISP
304
Software Approached ISP
305
Notes for ISP
305
In-Application-Programming (IAP)
306
IAP-Memory Boundary/Range
306
Update Data in IAP-Memory
306
Notes for IAP
307
ISP/IAP Register
307
ISP/IAP Sample Code
310
Page P SFR Access
312
Auxiliary Sfrs
317
SFR Figure(Page 0~F
317
SFR Bit Assignment (Page 0~F)
318
Auxiliary SFR Map
322
Auxiliary SFR Bit Assignment
322
Auxiliary SFR Register
324
Hardware Option
333
Application Notes
335
Power Supply Circuit
335
Reset Circuit
335
ICP and OCD Interface Circuit
335
In-Chip-Programming Function
336
On-Chip-Debug Function
337
Instruction Set
339
Ordering Information
342
Packaging Information
343
Top Marking
344
Reference Documents
345
Revise History
346
Contacts
347
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