Isp/Iap Flash Page Erase Mode - CMOSTEK CMT2380F17 Manual

Ultra low power sub-1ghz wireless mcu
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To do Page Erase (512 Bytes per Page)
Step 1: Set MS[2:0]=[0,1,1] in ISPCR register to select Page Erase Mode. Step 2: Fill page address in
IFADRH & IFADRL registers.
Step 3: Sequentially write 0x46h then 0xB9h to SCMD register to trigger an ISP processing.
To do Byte Program
Step 1: Set MS[2:0]=[0,1,0] in ISPCR register to select Byte Program Mode. Step 2: Fill byte address in
IFADRH & IFADRL registers.
Step 3: Fill data to be programmed in IFD register.
Step 4: Sequentially write 0x46h then 0xB9h to SCMD register to trigger an ISP processing.
To do Read
Step 1: Set MS[2:0]=[0,0,1] in ISPCR register to select Read Mode. Step 2: Fill byte address in IFADRH &
IFADRL registers.
Step 3: Sequentially write 0x46h then 0xB9h to SCMD register to trigger an ISP processing. Step 4: Now,
the Flash data is in IFD register.
The detailed descriptions of flash page erase, byte program and flash read in CMT2380F17 is listed in
the following sections:

28.2.1 ISP/IAP Flash Page Erase Mode

The any bit in flash data of CMT2380F17 only can be programmed to "0". If user would like to write a "1"
into flash data, the flash erase is necessary. But the flash erase in MG82F6D17 ISP/IAP operation only
support "page erase" mode, a page erase will write all data bits to "1" in one page. There are 512 bytes in one
page of MG82F6D17 and the page start address is aligned to A8~A0 = 0x000. The targeted flash address is
defined in IFADRH and IFADRL. So, in flash page erase mode, the IFADRH.0(A8) and IFADRL.7~0(A7~A0)
must be written to "0" for right page address selection. Figure 28–2 shows the flash page erase flow in ISPIAP
operation.
Rev0.1 | 299/347
CMT2380F17
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