CMOSTEK CMT2380F17 Manual page 292

R/W W
Reset V alue X
Bit 7: IGADCI, Ignore ADCI interrupt.
0: Enabled ADCI interrupt. Default is enabled. 1: Disable ADCI interrupt.
Bit 6: EADCWI, ADCWI interrupt enable. 0: Disable ADCWI interrupt.
1: Enable ADCWI interrupt to share the ADC interrupt vector.
Bit 5: SMPFIE, SMPF interrupt enable. 0: Disable SMPF interrupt.
1: Enable SMPF interrupt to share the ADC interrupt vector.
Bit 4~0: SIGN and AOS.3~0. The register value adjusts the ADC result in {ADCDH, ADCDL} for offset
cancellation. Software can dynamically collect the ADC offset value. Software can also stores the value in
MG82F6D17 IAP zone to use it as a constant parameter for ADC offset cancellation. The following table lists
the AD0ROC adjustment value for ADC transfer result.
{Sign, AOS.[3:0]}

ADCFG2： ADC Configuration Register 2
SFR Page = 2 only
SFR Address = 0xC3
7
Bit
Name
R/W
R/W
0
Reset V alue
Bit 7~0: SHT[7:0], extend ADC sample time. The value of SHT is 0~255 ADC clocks.

ADCFG3： ADC Configuration Register 3
SFR Page = 3 only
SFR Address = 0xC3
Bit
7
Name ADPS1
R/W R/W
Reset V alue 0
Bit 7~6: ADPS1~0, ADC Trigger Mode selection bit 3~2.
ADPS[1:0]
W W
X X
Value in {ADCDH, ADCDL}
0_1111 ADC transfer value + 15
0_1110 ADC transfer value + 14
...... ......
0_0010 ADC transfer value + 2
0_0001 ADC transfer value + 1
0_0000 ADC transfer value + 0
ADC transfer value – 1
1_1111
ADC transfer value – 2
1_1110
...... ......
ADC transfer value – 15
1_0001
ADC transfer value – 16
1_0000
6 5
R/W R/W
0 0
6 5
ADPS0 --
R/W W
1 0
0 0
0 1 Medium high power, medium high speed (default)
Rev0.1 | 292/347
R/W R/W
0 0
4 3
SHT[7:0]
R/W R/W
0 0
4 3
-- ARES1
W R/W
0 0
ADC Power Saving control
High power, high speed
CMT2380F17
R/W R/W
0 0
2 1
R/W R/W
0 0
2 1
ARES0 ADES0
R/W R/W
0 0
www.cmostek.com
R/W
0
0
R/W
0
0
--
W
0