CMOSTEK CMT2380F17 Manual

Ultra low power sub-1ghz wireless mcu
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Ultra Low Power Sub-1GHz Wireless MCU

MCU Features

1-T 80C51 CPU platform
16kB program area Flash with password access
protects. Default space configuration:
-
AP program space (13.5 kB, 0000h ~ 35FFh)
-
IAP data space (1.0 kB, 3600h ~ 39FFh)
-
ISP boot code space (1.5 kB, 3A00h ~ 3FFFh)
1 kB data memory
-
256-byte high-speed buffer
-
768-byte of extended RAM (XRAM)
-
Extended RAM (XRAM) supporting page access
On-chip debug interface (OCD)
Multiple power control modes: power-down mode, idle
mode, slow-frequency mode, sub-frequency mode,
RTC mode, watch mode, and monitor mode
-
All interrupts supporting to wake up the CPU
from IDLE mode
-
10 interrupt sources supporting to wake up the
CPU in power-down mode
-
Slow-frequency mode and sub-frequency mode
supporting low-speed MCU operation
-
RTC mode supporting real-time clock (RTC) to
wake up the CPU in power-down mode
-
Watch mode supporting watchdog (WDT) to
wake up the CPU in power-down mode
-
Monitor mode supporting BOD1 to wake up the
CPU in power-down mode
Operating frequency range: up to 25 MHz
-
External crystal oscillator mode, 0–12 MHz at
2.0–3.6 V and 0–25 MHz at 2.4–3.6 V
-
CPU operating frequency can reach 12 MHz at
1.8-3.6 V and 25 MHz at 2.2-3.6 V
-
When on-chip clock frequency multiplier (CKM)
is at 2.7–3.6 V, the CPU operating frequency
can reach 36 MHz.
Double data pointer
Interrupt control
-
16 interrupt sources, 4 priority levels
-
3 external interrupts nINT0/1/2, with filtering
-
All external interrupts supporting high/low or
rising/falling edge triggering
8-channel 12-bit single-ended ADC with a sampling
rate greater than 500 ksps
Copyright © By CMOSTEK
CMT2380F17
1 master/slave SPI serial interface, the rate reaching 12 MHz
2 master/slave two-wire serial interfaces: TWI0/I2C0
and STWI (SI2C)
1-channel DMA engine
-
P2P, M2P, P2M
-
Memory target: XRAM
-
Peripheral targets: UART0, UART1, SPI,
TWI0/I2C0, ADC12 and CRC16
-
Timer 5 and Timer 6 are applied by DMA; they
are independent timers when DMA is not
enabled.
Totally 9/11 timers/counters on-chip
-
RTC timer and WDT timer
-
Timer 0, 1, 2, 3
-
PCA0, programmable counter array 0
-
S0BRG and S1BRG
-
When timer 2/3 is used in separated mode,
there are a total of 11 timers
8 keyboard interrupts
1 enhanced UART0 and 1 normal UART1

RF Features

Operating frequency: 127-1020 MHz
Modulation and demodulation methods: (G)FSK,
(G)MSK, OOK
Data rate: 0.5-300 kbps
Sensitivity: -121 dBm @ 434 MHz, FSK
Receive current: 8.5 mA @ 434 MHz, FSK
Transmitting current: 72 mA @ 20 dBm, 434 MHz
Configurable FIFO up to 64-Byte

System Features

Operating voltage: 1.8 – 3.6 V
Operating temperature: -40 – 85 ℃
QFN40 5x5 packaging

Application

Automatic meter reading
Home security and building automation
Wireless sensor networks and industrial monitoring
ISM band data communication
Rev0.1 | 1/347
CMT2380F17
www.cmostek.com

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Summary of Contents for CMOSTEK CMT2380F17

  • Page 1: Mcu Features

    Home security and building automation rising/falling edge triggering   Wireless sensor networks and industrial monitoring 8-channel 12-bit single-ended ADC with a sampling rate greater than 500 ksps  ISM band data communication www.cmostek.com Copyright © By CMOSTEK Rev0.1 | 1/347...
  • Page 2: Description

    RSSI, manual fast frequency hopping, multi-channel input 12-bit high-speed ADC, etc. Leading the industry in the aspect of the smallest package size, the CMT2380F17 is ideal for IoT applications with critical requests in s ize constraints and power-efficiency.
  • Page 3 ± 10%, 0603 multilayer chip inductor Sunlord SDCL ± 10%, 0603 multilayer chip inductor Sunlord SDCL ± 10%, 0603 multilayer chip inductor Sunlord SDCL ± 10 ppm, SMD32*25 mm EPSON CMT2380F17, ultra-low power CMOSTEK sub-1GHz wireless MCU www.cmostek.com Rev0.1 | 3/347...
  • Page 4: Table Of Contents

    CMT2380F17 Table of Content MCU Features ..................................1 RF Features ..................................1 System Features ................................1 Application ..................................1 Description ..................................2 1 Electrical Specifications ............................11 1.1 Recommended Operating Conditions ......................... 11 1.2 Absolute Maximum Ratings..........................11 1.3 RF Power Consumption ............................12 1.4 Receiver ................................
  • Page 5 CMT2380F17 5.3.2 Indirect Addressing (IND) ........................49 5.3.3 Register Instruction (REG) ........................49 5.3.4 Register-Specific Instruction ........................49 5.3.5 Immediate Constant (IMM) ........................49 5.3.6 Index Addressing........................... 49 6 Memory Organization ..............................50 6.1 On-Chip Program Flash ............................50 6.2 On-Chip Data RAM ............................. 51 6.3 On-chip Expanded RAM (XRAM) ........................
  • Page 6 CMT2380F17 13.1 Brown-Out Detector ............................86 13.2 Power Saving Mode ............................86 13.2.1 Slow Mode ............................86 13.2.2 Sub-Clock Mode............................ 87 13.2.3 RTC Mode ............................. 87 13.2.4 Watch Mode ............................87 13.2.5 Monitor Mode ............................87 13.2.6 Idle Mode .............................. 87 13.2.7...
  • Page 7 CMT2380F17 16.2.1 Timer 2 Mode 0 (Auto-Reload and External Interrupt) ................ 141 16.2.2 Timer 2 Mode 1 (Auto-Reload with External Interrupt) ................ 142 16.2.3 Timer 2 Mode 2 (Capture) ........................143 16.2.4 Timer 2 Mode 3 (Capture with Auto-Zero) ................... 144 16.2.5...
  • Page 8 CMT2380F17 18.6 Automatic Address Recognition ........................204 18.7 Baud Rate Setting ............................. 206 Baud Rate Selection in S0 ....................... 206 18.7.1 18.7.2 Baud Rate in Mode 0 .......................... 206 18.7.3 Baud Rate in Mode 2 .......................... 207 18.7.4 Baud Rate in Mode 1 & 3 ........................208 18.7.4.1 Using Timer 1 as the Baud Rate Generator ..................
  • Page 9 27.3 How to read IVR (1.4V) ADC Prestored value ....................296 28 ISP and IAP ................................298 28.1 CMT2380F17 Flash Memory Configuration ...................... 298 28.2 CMT2380F17 Flash Access in ISP/IAP ......................298 28.2.1 ISP/IAP Flash Page Erase Mode ......................299 28.2.2...
  • Page 10 CMT2380F17 28.6 ISP/IAP Sample Code ............................310 29 Page P SFR Access ..............................312 30 Auxiliary SFRs ................................. 317 30.1 SFR Figure(Page 0~F) ..........................317 30.2 SFR Bit Assignment (Page 0~F) ........................318 30.3 Auxiliary SFR Map (Page P) ..........................322 30.4 Auxiliary SFR Bit Assignment (Page P) ......................
  • Page 11: Electrical Specifications

    [2]. The CMT2380F17 is a high performance RF integrated circuit. The operation and assembly of this chip should only be performed on a workbench with good ESD protection.
  • Page 12: Rf Power Consumption

    CMT2380F17 1.3 RF Power Consumption Parameter Symbol Condition Min. Typ. Max. Unit Sleep mode, sleep counter off Sleep current SLEEP Sleep mode ,sleep counter on Standby current Crystal oscillator on 1.45 Standby 433 MHz RFS current 868 MHz 915 MHz...
  • Page 13 CMT2380F17 Parameter Symbol Condition Min. Typ. Max. Unit DR = 10 kbps, F = 10 kHz(low-power -115 configuration) -113 DR = 20 kbps, F = 20 kHz DR = 20 kbps, F = 20 kHz (low-power -112 configuration) DR = 50 kbps, F...
  • Page 14: Transmitter

    CMT2380F17 Parameter Symbol Condition Min. Typ. Max. Unit continuous wave interference DR = 10 kbps, F = 10 kHz, ± 10 MHz offset, continuous wave interference DR = 10 kbps, F = 10 kHz, 1 MHz and Input 3 order...
  • Page 15: Rf Operating Mode Switching Time

    = 915 MHz harmonic,+13 dBm P Notes: [1] The harmonic level mainly depends on the matching network. Above parameters are measured based on the CMT2380F17-EM, users may get different results on their PCB designs. 1.6 RF Operating Mode Switching Time Parameter Symbol Condition Min.
  • Page 16 CMT2380F17 Parameter Symbol Condition Min. Typ. Max. Unit 500 kHz deviation -111 dBc/Hz 1MHz deviation -121 dBc/Hz 10 MHz deviation -130 dBc/Hz www.cmostek.com Rev0.1 | 16/347...
  • Page 17: Requirement On Crystals For Rf Section

    CMT2380F17 1.8 Requirement on Crystals for RF Section Parameter Symbol Condition Min. Typ. Max. Unit Crystal frequency XTAL Crystal frequency tolerance Load capacitance LOAD Ω Crystal startup time XTAL Notes: [1]. An external reference clock can be used to drive the XI pin directly through a coupling capacitor if such a clock is available.
  • Page 18: Controller Power Consumption Characteristics

    CMT2380F17 1.10 Controller Power Consumption Characteristics Parameter Symbol Condition Note Typ. Max. Unit SYSCLK = 32MHz @ IHRCO with PLL 10.5 SYSCLK = 24MHz @ IHRCO with PLL Normal mode SYSCLK = 12MHz @ IHRCO operating current SYSCLK = 12MHz @ IHRCO, V =3.3V with...
  • Page 19: Controller Ilrco Characteristics

    CMT2380F17 1.13 Controller ILRCO Characteristics Parameter Symbol Condition Note Typ. Max. Unit Supply power voltage ILRCO frequency TA = +25° C TA = +25° C ILRCO frequency deviation TA = -40° C~+85° C Notes: [1] The data is based on the characteristics, not from product test.
  • Page 20: Ivr Characteristics

    CMT2380F17 Parameter Symbol Condition Note Typ. Max. Unit Ω = 3.3V Input sampling switch Ω resistance = 2.7V 1050 CH0(V )CH1(V resistor divider) Switch from VDD to resistor divider (VDD/2) CH0(V )CH1(V resistor divider) CH0(GND)CH1(V /2, 51K resistor divider) Switch from GND to resistor divider (VDD/2) CH0(GND)CH1(V...
  • Page 21: Controller Serial Port Timing Characteristics

    CMT2380F17 1.18 Controller Serial Port Timing Characteristics URM0X3 = 0 URM0X3 = 1 Unit Parameter Symbol Condition Min. Max. Min. Max. Serial Port Clock Cycle Time XLXL SYSCLK 10T-20 2T-20 Output Data Setup to Clock Rising Edge QVXH T-10 T-10...
  • Page 22 CMT2380F17 Clock Cycle SPICLK(CPOL=0) SPICLK(CPOL=1) MISO MOSI Figure 1-2. SPI Master Transfer Waveform with CPHA=0 Clock Cycle SPICLK(CPOL=0) SPICLK(CPOL=1) MISO MOSI Figure 1-3. SPI Master Transfer Waveform with CPHA=1 Clock Cycle SPICLK(CPOL=0) SPICLK(CPOL=1) MOSI MISO Figure 1-4. SPI Slave Transfer Waveform with CPHA=0 www.cmostek.com...
  • Page 23: Receive Current And Supply Voltage Correlation

    CMT2380F17 Clock Cycle SPICLK(CPOL=0) SPICLK(CPOL=1) MOSI MISO Figure1-5. SPI Slave Transfer Waveform with CPHA=1 1.20 Receive Current and Supply Voltage Correlation Test Conditions: Freq=434MHz / 868MHz, Fdev=10KHz, BR=10Kbps www.cmostek.com Rev0.1 | 23/347...
  • Page 24: Correlation Among Receive Current, Supply Voltage And Temperature

    CMT2380F17 1.21 Correlation Among Receive Current, Supply Voltage and Temperature Test Conditions: Freq = 434MHz, Fdev = 10KHz, BR = 10Kbps Test Conditions: Freq = 868MHz, Fdev = 10KHz, BR = 10Kbps www.cmostek.com Rev0.1 | 24/347...
  • Page 25: Receive Sensitivity And Supply Voltage Correlation

    CMT2380F17 1.22 Receive Sensitivity and Supply Voltage Correlation Test Conditions: FSK modulation, DEV = 10KHz, BR = 10Kbps 1.23 Receive Sensitivity and Temperature Correlation Test Conditions: FSK modulation, DEV = 10KHz, BR = 10Kbps www.cmostek.com Rev0.1 | 25/347...
  • Page 26: Transmit Power And Supply Voltage Correlation

    CMT2380F17 1.24 Transmit Power and Supply Voltage Correlation : Test Conditions Freq = 434 MHz, 20 dBm & 13 dBm matching network respectively : Test Conditions Freq = 868MHz, 20dBm / 13dBm matching network www.cmostek.com Rev0.1 | 26/347...
  • Page 27: Phase Noise

    CMT2380F17 1.25 Phase Noise www.cmostek.com Rev0.1 | 27/347...
  • Page 28: Pin Description

    QFN40_5x5 RF_DGND P1.5 RF_DVDD P1.1 GPIO3 P1.0 P3.3 MCU_VDD P3.4 MCU_VR0 Figure1. CMT2380F17 Pin Arrangement Diagram Table 2. CMT2380F17 Pin Description Pin # Pin Name Description Analog Chip substrate, must connect to ground No connection 2 - 3 RFIP/RFIN Analog...
  • Page 29 CMT2380F17 Pin # Pin Name Description P3.4 Port P3.4 T0/T0CKO External clock input/programmable clock output of Timer 0 CEX3 External IO of PCA0 module 3 T3EX External control input signal of Timer 3 External clock input signal of Timer 5...
  • Page 30 CMT2380F17 Pin # Pin Name Description AIN0 Channel 0 of ADC analog input KBI0 Channel 0 of keyboard input T2/T2CKO Output signal of Timer 2 external clock input/programmable clock RxD1 RxD signal of UART1 module P1.1 Port P1.1 AIN1 Channel 1of ADC analog input...
  • Page 31 CMT2380F17 Pin # Pin Name Description TxD0 TxD signal of UART0 module SCLK RF SPI clock RF SPI data input/output, connecting to 10 kΩ pull-up resistor externally RF SPI chip selection for register access FCSB RF SPI chip selection for FIFO access...
  • Page 32: Chip Structure

     1-T High Performance 80C51 Microprocessor The CMT2380F17 is a single-chip microcontroller based on a high performance 1-T architecture 80C51 CPU that executes instructions in 1~7 clock cycles (about 6~7 times the rate of a standard 8051 device), and has an 8051 compatible instruction set. Therefore at the same performance as the standard 8051, the www.cmostek.com...
  • Page 33 CMT2380F17 can operate at a much lower speed and thereby greatly reduce the power consumption. The CMT2380F17 has 16K bytes of embedded Flash memory for code and data. The Flash memory can be programmed either in serial writer mode (via ICP, In-Circuit Programming) or in In-System Programming mode.
  • Page 34 Monitor mode:detect the voltage in power-down mode, and reset when the voltage is particularly low. The CMT2380F17 is equipped with a Megawin proprietary On-Chip Debug (OCD) interface for In-Circuit Emulator (ICE). The OCD interface provides on-chip and in-system non-intrusive debugging without any target resource occupied.
  • Page 35: Sub-Ghz Transceiver

    4.2 Receiver An ultra-low power, high performance low IF OOK, FSK receiver is built in the CMT2380F17. It follows processing steps as: 1) The RF signal sensed by the antenna is amplified by the low noise amplifier. 2) The signal is down-converted to the intermediate frequency by the quadrature mixer and then filtered by the image rejection filter.
  • Page 36: Transceiver Crystal Oscillator

    4.5 Transceiver Built-in Low Frequency Oscillator (LPOSC) The CMT2380F17 RF system integrates a sleep timer driven by a 32 kHz low power oscillator (LPOSC). When this function is enabled, the timer periodically wakes up the chip from sleep mode. Sleep time can be configured from 0.03125 ms to 41,922,560 ms when the chip is in periodical operating mode.
  • Page 37: Transceiver Built-In Low Battery Detection

    Figure 4-3. RSSI Measuring and Comparing Circuit Structure The CMT2380F17 offers RSSI to meet the qualitative analysis requirements of users generally. However more accurate RSSI measurement results are needed in case of quantitative analysis, therefore users need to perform production calibration based on actual solutions.
  • Page 38: Receiver Clock Data Recovery (Cdr)

    Therefore, CDR takes a simple but critical role. The CMT2380F17 receiver supports three CDR systems according to different application requirements:  COUNTING system This system is designed for the case where the data rate is relatively accurate.
  • Page 39: Fast Manual Frequency Hopping

    4.11.1 Transceiver SPI Interface Timing The RF system of CMT2380F17 communicates with the controller section via a 4-wire SPI port (FCSB, CSB, SDA and SCLK). The low active CSB is the chip selection signal used to access the registers. The low active FCSB is the chip selection signal used to access the FIFO.
  • Page 40: Transceiver Fifo Interface Timing

    CMT2380F17 > 0.5 SCLK cycle > 0.5 SCLK cycle FCSB SCLK r/w = 0 register address register write data Figure 4-6. Transceiver SPI Write Register Timing 4.11.2 Transceiver FIFO Interface Timing By default, the transceiver provides two independent 32-byte FIFOs for RX and TX. The RX FIFO is used to store received data in RX mode, and the TX FIFO is to store data to be transmitted in TX mode.
  • Page 41: Transceiver Operating Status, Timing, And Power Consumption

    CMT2380F17 > 1 SCLK cycle > 2 us > 4 us > 1 SCLK cycle > 2 us FCSB SCLK FIFO write data FIFO write data Figure 4-8. SPI Write FIFO Timing The transceiver provides enriched FIFO-related interrupt sources helping for efficient operation of the chip. The Rx and Tx-related FIFO interrupt timing is shown in the figure below.
  • Page 42 CMT2380F17 be written later by writing XTAL_STB_TIME <2:0>. The chip stays in the IDLE state until the crystal is stable. After the crystal is stabilized, the chip will leave IDLE and begin calibration for each module. After calibration, the chip will stay at SLEEP, waiting for the user to do initialization configuration.
  • Page 43 CMT2380F17 Table 4-1. Transceiver Status and Module Startup Table Switch Optional Startup Status Binary Code Startup Module Command Module IDLE 0000 soft_rst SPI, POR SLEEP 0001 go_sleep SPI, POR, FIFO LFOSC, Sleep Timer STBY 0010 go_stby SPI, POR, XTAL, FIFO...
  • Page 44: Transceiver Gpio Function And Interrupt Mapping

    CMT2380F17 be larger than that in STBY. As the PLL is already locked to the RX frequency point in RFS status, it cannot be switched to TX. Switching from STBY to RFS requires approximately 350us for PLL calibration and settling. Switching from SLEEP to RFS requires more time to wait for the crystal startup and stabilizing for a while.
  • Page 45 CMT2380F17 Table 4-3. Transceiver Interrupt Mapping Clear Name INT1_SEL Description Method RX_ACTIVE 00000 Indicates that the interrupt is ready to enter RX or has entered RX, Auto which is 1 in the PLL calibration and RX status, otherwise 0. TX_ACTIVE...
  • Page 46 CMT2380F17 RX_ACTIVE RSSI_VLD_FLG PREAM_OK_CLR PREAM_OK_EN Preamble OK Interrupt Source PREAM_OK_FLG SYNC_OK_CLR SYNC_OK_EN INT1_CTL <4:0> Sycn Word OK Interrupt Source SYNC_OK_FLG 00000 NODE_OK_CLR NODE_OK_EN 00001 Node ID OK 00010 Interrupt Source NODE_OK_FLG 00011 00100 CRC_OK_CLR CRC_OK_EN 00101 CRC OK Interrupt Source...
  • Page 47: 80C51 Cpu Function Description

    CMT2380F17 5 80C51 CPU Function Description 5.1 CPU Register  PSW: Program Status Word SFR Page = 0~F SFR Address = 0xD0 Name Reset V alue CY: Carry bit. AC: Auxiliary carry bit. F0: General purpose flag 0. RS1: Register bank select bit 1.
  • Page 48: Cpu Timing

    This register serves as a second accumulator for certain arithmetic operations. 5.2 CPU Timing CMT2380F17 is a single-chip microcontroller based on a high performance 1-T architecture 80C51 CPU that has an 8051 compatible instruction set, and executes instructions in 1~7 clock cycles (about 6~7 times www.cmostek.com...
  • Page 49: Cpu Addressing Mode

    CMT2380F17 the rate of a standard 8051 device). It employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. The instruction timing is different than that of the standard 8051. In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length.
  • Page 50: Memory Organization

    Program memory (ROM) can only be read, not written to. There can be up to 16K bytes of program memory. In the CMT2380F17, all the program memory are on-chip Flash memory, and without the capability of accessing external program memory because of no External Access Enable (/EA) and Program Store Enable (/PSEN) signals designed.
  • Page 51: On-Chip Data Ram

    CMT2380F17 6.2 On-Chip Data RAM Figure 6–2 shows the internal and external data memory spaces available to the CMT2380F17 user. Internal data memory can be divided into three blocks, which are generally referred to as the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128 bytes of SFR space. Internal data memory addresses are always 8-bit wide, which implies an address space of only 256 bytes.
  • Page 52: On-Chip Expanded Ram (Xram)

    @Ri” and “MOVX @DPTR”, respectively. Thus the CMT2380F17hardware can access them correctly. 6.4 Off-Chip External Data Memory access The off-chip external data memory access function is not supported in CMT2380F17. 6.5 Declaration Identifiers in a C51-Compiler The declaration identifiers in a C51-compiler for the various CMT2380F17memory spaces are as follows: data 128 bytes of internal data memory space (00h~7Fh);...
  • Page 53 Paged (256 bytes) external data or on-chip eXpanded RAM; duplicates the classic 80C51 256 bytes memory space addressed via the “MOVX @Ri” instruction. The CMT2380F17 has 256 bytes of on-chip pdata memory which is shared with on-chip xdata memory.
  • Page 54: Xram Access

    CMT2380F17 7 XRAM Access The CMT2380F17 MCUs include 768 bytes of on-chip RAM mapped into the external data memory space (XRAM). The external memory space may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using the MOVX indirect addressing mode using R0 or R1. If the MOVX instruction is used with an 8-bit address operand (such as @R1), then the high byte of the 16-bit address is provided by the XRAM Page Select Register (XRPS).
  • Page 55: Movx On 8-Bit Address With Xrps

    CMT2380F17 Bit 0: DPS, DPTR select bit. Use to switch between DPTR0 and DPTR1. 0: Select DPTR0. 1: Select DPTR1. Selected DPTR DPTR0 DPTR1  DPL: Data Pointer Low SFR Page = 0~F SFR Address = 0x82 Name DPTR[7:0] Reset V alue The DPL register is the low byte of the 16-bit DPTR.
  • Page 56 (reserved) bits of the register are always zero, the XRPS determines which page of XRAM is accessed. In CMT2380F17, XRPS indexes the three pages 256-byte RAM. For Example: If XRPS = 0x01, addresses 0x0100 through 0x01FF in XRAM will be accessed.。...
  • Page 57: Direct Memory Access Controller (Dma)

    Figure 8-1. DMA DMA Access Diagram 8.1 DMA Structure In CMT2380F17, the DMA controller provides one channel DMA to support 3 transfer types: transfer the data from XRAM to peripheral, from peripheral to XRAM and from peripheral to peripheral. DMADS0 register in DMA channel 0 defines the DMA transfer type to configure DMA controller behavior and defines the data path to generate the SFR address on peripheral access.
  • Page 58: Dma Operation

    The DMA controller is configured with user software. The setup and operation of the DMA is discussed in the following sections. 8.2.1 DMA Transfer Types The DMA controller in CMT2380F17 supports 3 type data transfer as following list::  M2P: XRAM to Peripheral ...
  • Page 59: Dma Transfer Mode

    XRAM 8.2.2 DMA Transfer Mode The DMA controller in CMT2380F17 only supports block transfer mode. After DMA trigger active, DMA controller start to move data until the overflow event happened on DMA Current Transfer Count. That is one trigger input to activate a block data transfer by DMA controller.
  • Page 60: Start A Dma Transfer

    XRAM memory space. 8.2.4 Start a DMA Transfer It is an easy handling DMA controller in CMT2380F17.To starting a DMA transfer, software must issue the following sequence to construct a DMA operation: 1. Configure DMADS0 to determine the DMA transfer type and DMA data path on source and destination.
  • Page 61: Dma Loop Mode

    8.2.8 Error Handling in DMA There is no any error handling function in the DMA controller, software will take care on: A. Current Address cannot over the XRAM boundary. In CMT2380F17, XRAM boundary is 768 bytes (02FFH). B. Cannot support the even/odd parity check and generation on S0 and S1.
  • Page 62: Dma Register

    CMT2380F17 DMA Current Transfer Count T5IE (0,0) SYSCLK /12 16-bit Up Counter T5SCT (0,1) T5 Pin Overflow (1,0) (8 Bits) (8 Bits) SYSCLK (1,1) T2EXI Reload T5CKS.1~0 (0,0) Interrupt TLR5 THR5 "1" (0,1) DMA_CLK INT0ET DMA Base Transfer Count T6IE...
  • Page 63 CMT2380F17 Reset V alue Bit 7~4: Reserved. Software must write “0” on these bits when DMACR0 is written. Bit 3: DMAE0, DMA Enable 0. 0: Clear to disable DMA operation. 1: Set to enable DMA operation. Bit 2: DMAS0. DMA transfer Start 0.
  • Page 64: Timer5 Register

    CMT2380F17  DMADS0: DMA Data path Selection Register 0 SFR Page = 9 only SFR Address = 0x94 Name DSS30 DSS20 DSS10 DSS00 DDS30 DDS20 DDS10 DDS00 Reset V alue Bit 7~4: DMA data Source Selection. Bit 3~0: DMA data Destination Selection.
  • Page 65 CMT2380F17 Disable INT0ET INT2ET KBIET  TL5: Timer 5 Low byte Register SFR Page = 3 Only SFR Address = 0xCC Name TL5 [7:0] Reset V alue  TH5: Timer 5 High byte Register SFR Page = 3 Only SFR Address = 0xCD...
  • Page 66: Timer 6 Register

    CMT2380F17  TLR5: Timer 5 Low byte Reload Register SFR Page = 3 Only SFR Address = 0xCA Name TLR5 [7:0] Reset V alue  THR5: Timer 5 High byte Reload Register SFR Page = 3 Only SFR Address = 0xCB...
  • Page 67 CMT2380F17 SFR Page = 4 Only SFR Address = 0xCC Name TL6 [7:0] Reset V alue TH6: Timer 6 High byte Register SFR Page = 4 Only SFR Address = 0xCD Name TH6 [7:0] Reset V alue  TLR6: Timer 6 Low byte Reload Register...
  • Page 68: System Clock

    The CMT2380F17 device includes a Clock Multiplier (CKM) to generate the high speed clock for system clock source. CKM applied in CMT2380F17 is shown in Figure 9–1 and its typical input frequency is around 6MHz. Before enable CKM, software must configure the CKMIS1~0 (CKCON.5~4) to get the reasonable CKMI frequency for CKM input source.
  • Page 69: Clock Source Switching

    Internal Low-frequency RC Oscillator (ILRCO) and External Clock Input. Figure 9–1 shows the structure of the system clock in CMT2380F17. The CMT2380F17 always boots from IHRCO on 12MHz. OSCS[1:0] are used to select the clock source by software setting, but the software need to wait until the clock be settle before switch the clock source.。...
  • Page 70: Clock Register

    CMT2380F17  Continue program execution……… 9.5 Clock Register CKCON0: Clock Control Register 0 SFR Page = 0~F & P SFR Address = 0xC7 Name ENCKM CKMIS1 CKMIS0 CCKS SCKS2 SCKS1 SCKS0 Reset V alue Bit 7: AFS, Alternated Frequency Selection.
  • Page 71 CMT2380F17 Bit 2~0: SCKS2 ~ SCKS0, programmable System Clock Selection. SCKS[2:0] System Clock (SYSCLK) 0 0 0 MCKDO/1 0 0 1 MCKDO/2 0 1 0 MCKDO/4 0 1 1 MCKDO/8 1 0 0 MCKDO/16 1 0 1 MCKDO/32 1 1 0...
  • Page 72 CMT2380F17 Bit 5: FWKP, MCU Fast wake up control 0: Select MCU for normal wakeup time about 120us from power-down mode. 1: Select MCU for fast wakeup time about 30us from power-down mode. Bit 4: WDTFS. WDT overflow source selection.
  • Page 73 CMT2380F17 SFR Page = P Only SFR Address = 0x4C Name IAPO HSE1 IORCTL RSTIO OCDE Reset V alue Bit 7: HSE, High Speed operation Enable. 0: Select CPU running in lower speed mode (FCPUCLK ≤ 6MHz) which is slow down internal circuit to reduce power consumption.
  • Page 74: Watch Dog Timer (Wdt)

    The WDT consists of a 8-bit free-running counter, a 8-bit prescaler and a control register (WDTCR). Figure 10–1 shows the WDT structure in CMT2380F17. There are four selections for WDT clock source. The clock source must be configured before WDT enabled.
  • Page 75: Wdt Register

    CMT2380F17 10.3 WDT Register  WDTCR: Watch-Dog-Timer Control Register SFR Page = 0~F & P SFR Address = 0xE1 POR = XXX0-XXXX (0000-0111) Name WREN CLRW WIDL PS[2:0] Reset V alue Bit 7: WREN, WDT Reset Enable. The initial value can be changed by hardware option, WRENO.
  • Page 76 CMT2380F17 WDT Period Note 分频值 PS[2:0] (clock source = ILRCO) 0 0 0 0.125 ms + 120us 0 0 1 0.25 ms + 120us 0 1 0 0.5 ms + 120us 0 1 1 1 ms + 120us 1 0 0...
  • Page 77: Wdt Hardware Option

    CMT2380F17  CKCON3: Clock Control Register 3 SFR Page = P only SFR Address = 0x41 Name WDTCS[1:0] FWKP WDTFS MCKD1 MCKD0 Reset V alue Bit 7~6: WDTCS1~0, WDT Clock Source selection [1:0]. WDTCS1~0 WDT Clock Source ILRCO ECKI(P6.0) SYSCLK/12 S0TOF Bit 4: WDTFS.
  • Page 78: Real-Time-Clock (Rtc)/System-Timer

    11 Real-Time-Clock (RTC)/System-Timer The CMT2380F17 has a simple Real-Time clock that allows a user to continue running an accurate timer while the rest of the device is powered-down. The Real-Time clock can be a wake-up or an interrupt source.
  • Page 79 CMT2380F17 (/2^15) RTC Prescaleer RTCPS[14] (0,0,0) (0,0,0,0) ECKI (P6.0) RTCPS[0:4] RTCPS[5:8] RTCPS[13] (0,0,1) (0,0,0,1) ILRCO RTCPS[9:12] RTCPS[12] (0,1,0) (0,0,1,0) WDTPS RTCPS[13:14] RTCPS[11] (0,1,1) (0,0,1,1) WDTOF RTCPS[10] (1,0,0) (0,1,0,0) SYSCLK (1,0,1) SYSCLK/12 RCSS[2:0] RTCPS[1] (1,1,0,1) RPCS[0] RPCS[1] RPCS[2] RTCPS[0] (1,1,1,0) RTCPSI...
  • Page 80 CMT2380F17 Reset V alue Bit 7~6: RTCCS.1~0, RTC Clock Selection. Default is “01”. RTCCS3~0 Clock Source RTC Interrupt Duration Minimum Step 1S ~ 64S 0 0 0 0 RTCPS[14] (/2^15) when P6.0 = 32768Hz 0.5S 0.5S ~ 32S 0 0 0 1 RTCPS[13] (/2^14) when P6.0 = 32768Hz...
  • Page 81 CMT2380F17 Reset V alue Bit 4: RTCF, RTC overflow flag. 0: This bit must be cleared by software writing “1” on it. Software writing “0” is no operation. 1: This bit is only set by hardware when RTCCT overflows. Writing “1” on this bit will clear RTCF.
  • Page 82: System Reset

    During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector, 0000H, or ISP start address by OR setting. The CMT2380F17 has 7 sources of reset: power-on reset, external reset, software reset, illegal address reset, brown-out reset 0, brown-out reset 1 and WDT reset.
  • Page 83: Note: Pof0 Must Be Cleared By Software

    CMT2380F17  PCON0: Power Control Register 0 SFR Page = 0~F & P POR = 0001-0000, 复位值= 000X-0000 SFR Address = 0x87 Name SMOD[1:0] POF0 GF[1:0] Reset V alue Bit 4: POF0, Power-On Flag 0. 0: The flag must be cleared by software to recognize next reset type.
  • Page 84: Software Reset

    1: This bit is only set by hardware if a Software Reset occurs. Writing “1” on this bit will clear SWRF. 12.5 Brown-Out Reset In CMT2380F17, there are two Brown-Out Detectors (BOD0 & BOD1) to monitor VDD power. BOD0 services the fixed detection level at VDD=1.7V. BOD1 detects the VDD level by software selecting 4.2V, 3.7V, 2.4V or 2.0V.
  • Page 85: Wdt Reset

    1: This bit is only set by hardware when WDT overflows. Writing “1” on this bit will clear WDTF. If WREN (WDTCR.7) is set, WDTF indicates a WDT Reset occurred. 12.7 Illegal Address Reset In CMT2380F17, if software program runs to illegal address such as over program ROM limitation, it triggers a RESET to CPU. www.cmostek.com...
  • Page 86: Power Management

    CKCON2, CKCON3, CKCON4, CKCON5, PCON0, PCON1, PCON2, PCON3, RTCCR and WDTCR register. 13.1 Brown-Out Detector In CMT2380F17, there are two Brown-Out Detectors (BOD0 & BOD1) to monitor VDD power. Figure 13–1 shows the functional diagram of BOD0 and BOD1. BOD0 services the fixed detection level at VDD=1.7V and BOD1 detects the software selection levels (4.2V/3.7V/2.4V/2.0V) on VDD.
  • Page 87: Sub-Clock Mode

    Clock”), the user could put the MCU speed down to 250Hz slowest. 13.2.3 RTC Mode The CMT2380F17 has a simple RTC module that allows a user to continue running an accurate timer while the rest of the device is powered-down. In RTC mode, the RTC module behaves a “Clock” function and can be a wake-up source from chip power down by RTC overflow rate.
  • Page 88: Power-Down Mode

    WDTCR.ENW SFIE.WDTFIE Overflow ILRCO WDTF PCON0.PD WDT Reset WDTCR.NSW WDTCR.WREN RESET Wakeup External Reset PCON2.BO1RE BOD1 Reset EIE1.ESF BOD1 Wakeup SFIE.BOF1IE PCON2.EBOD1 BOD1 BOF1 PCON0.PD PCON2.AWBOD1 Figure 13-2. Wakeup structure of Power Down mode of CMT2380F17 www.cmostek.com Rev0.1 | 88/347...
  • Page 89: Interrupt Recovery From Power-Down

    Idle should not be one that writes to a port pin or to external memory. 13.2.10 KBI wakeup Recovery from Power-down The Keypad Interrupt of CMT2380F17, KBI.7~0 have wakeup CPU capability that are enabled by the control registers in KBI module. OR software can configure the KBI inputs on different port pins. Please refer Section “30 Auxiliary SFRs”...
  • Page 90 CMT2380F17 Bit 4: POF0, Power-On Flag 0. 0: This bit must be cleared by software writing one to it. 1: This bit is set by hardware if a Power-On Reset occurs. Bit 1: PD, Power-Down control bit. 0: This bit could be cleared by CPU or any exited power-down event. 1: Setting this bit activates power down operation.
  • Page 91 CMT2380F17  PCON2: Power Control Register 2 SFR Page = P Only SFR Address = 0x44 Name AWBOD1 BO1S[1:0] BO1RE EBOD1 BO0RE Reset V alue Bit 7: AWBOD1, Awaked BOD1 in PD mode. 0: BOD1 is disabled in power-down mode.
  • Page 92 CMT2380F17  PCON3: Power Control Register 3 SFR Page = P Only SFR Address = 0x45 POR = 0xxx-xxxx Name IVREN Reset V alue Bit 7: IVREN, Internal Voltage Reference Enable. 0: Disable on-chip IVR (1.4V). 1: Enable on-chip IVR (1.4V).
  • Page 93: Configurable I/O Ports

    14.1 IO Structure The I/O operating modes are distinguished two groups in CMT2380F17. The first group is only for Port 3 to support four configurations on I/O operating. These are: quasi-bidirectional (standard 8051 I/O port), push-pull output, input-only (high-impedance input) and open-drain output. The Port 3 default setting is quasi-bidirectional mode with weakly pull-up resistance.
  • Page 94: Port 3 Push-Pull Output Structure

    CMT2380F17 14.1.2 Port 3 Push-Pull Output Structure The push-pull output configuration on Port 3 has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port register contains a logic “1”. The push-pull mode may be used when more source current is needed from a port output.
  • Page 95: General Analog Input Only Structure

    CMT2380F17 Figure 14-4. Port 3 Open-Drain Output 14.1.5 General Analog Input Only Structure The analog-input-only configuration on general port pins is the default setting. For ADC or Analog Comparator input application, user may keep the port setting in this configuration. If apply the port pin to digital function, user must program the port pin to associated configuration.
  • Page 96: General Port Digital Input Configured

    Figure 14-8. General Push-Pull Output 14.1.10 Port Pin Output Driving Strength Selection The I/O of the CMT2380F17 has two driving strength can be selected for different kinds of the application to match the output impedance. Please reference 14.2.6 Port Output Driving Strength Control Register.。...
  • Page 97: Port 1 Register

    CMT2380F17 Figure 14-1. Port 3 Configuration Settings P3M0.y P3M1.y Port Mode Quasi-Bidirectional (default) Push-Pull Output Input Only (High Impedance Input) Open-Drain Output Note: Where y=0~7 (port pin). The registers P3M0 and P3M1 are listed in each port description. Other general port pins also support four operating modes, as shown in Table 14–3. Two mode registers select the I/O type for each port pin and setting to analog-input-only on these port pins after system reset.
  • Page 98: Port 2 Register

    CMT2380F17  P1M0: Port 1 Mode Register 0 SFR Page = 0~F SFR Address = 0x91 Name P1M0.7 P1M0.6 P1M0.5 P1M0.1 P1M0.0 Reset V alue  P1M1: Port 1 Mode Register 1 SFR Page = 0 only SFR Address = 0x92 Name P1M1.7...
  • Page 99: Port 3 Register

    CMT2380F17  P2M1: Port 2 Mode Register 0 SFR Page = 0 only SFR Address = 0x95 Name P2M1.4 P2M1.2 Reset V alue 14.2.3 Port 3 Register  P3: Port 3 Register SFR Page = 0~F SFR Address = 0xB0 Name P3.5...
  • Page 100: Port 4 Register

    CMT2380F17  AUXR11:Auxiliary Register 11 SFR Page = 8 only SFR Address = 0xA4 Name P30AM C0M0 C0OFS Reset V alue Bit 7: P30AM, P3.0 Analog input Mode enable. 0: The P3.0 GPIO mode is controlled by P3M0 and P3M1.
  • Page 101: Port 6 Register

    Reset V alue 14.2.6 Port Output Driving Strength Control Register In CMT2380F17, all port pins have two driving strength selection by software configured except P4.7, P6.1 and P6.0. Please refer to get the driving strength information on the port pins.
  • Page 102 CMT2380F17 1: Select the P3.3 ~ P3.0 output with low driving strength. Bit 5: P2DC1, Port 2 output driving strength control on high nibble. 0: Select the P2.7 ~ P2.4 output with high driving strength. 1: Select the P2.7 ~ P2.4 output with low driving strength.
  • Page 103: Port Output Fast Driving Control Register

    Bit 0: reserved bit. When writing the PDRVC1 register, the software bit must write to "0". 14.2.7 Port Output Fast Driving Control Register In CMT2380F17, all port pins have two driving speed selection by software configured except P4.7. Please refer to get the driving strength information on the port pins.
  • Page 104: Port Function Redirection

    CMT2380F17  P1FDC:Port 1 Fast Driving Control Register SFR Page = 8 only SFR Address = 0x92 Name P1FDC.7 P1FDC.6 P1FDC.5 P1FDC.1 P1FDC.0 Reset V alue Bit 7~0: Port 1 output fast driving control could be only set/cleared by CPU. 0: Disable fast driving on port pin output.
  • Page 105 CMT2380F17 Bit 7~6: P6.0 function configured control bit 1 and 0. The two bits only act when internal RC oscillator (IHRCO or ILRCO) is selected for system clock source. In external clock input mode, P6.0 is the dedicated clock input pin. In internal oscillator condition, P6.0 provides the following selections for GPIO or clock source generator.
  • Page 106 CMT2380F17 Bit 7~6: T2PS1~0, Timer 2 Port pin Selection [1:0]. T2PS1~0 T2/T2CKO T2EX P1.0 P1.1 P3.0 P3.1 P6.0 P3.5 P4.5 P4.4 Bit 5~4: T1PS1~0, Timer 1 Port pin Selection [1:0]. T1PS1~0 T1/T1CKO P3.5 P4.5 P1.7 P3.3  AUXR5:Auxiliary Register 5...
  • Page 107 CMT2380F17 Bit 2: C0PS0, PCA0 Port pin Selection 0. C0PS0 CEX0 CEX2 CEX4 P2.2 P2.4 P1.7 P3.0 P2.4 P3.1 Bit 1: ECIPS0, PCA0 ECI Port pin Selection0. ECIPS0 P4.4 P1.6 Bit 0: C0COPS, PCA0 Clock Output (C0CKO) port pin Selection.
  • Page 108 CMT2380F17 SFR Page = 4 only SFR Address = 0xA4 Name POE5 POE4 C0CKOE SPI0M0 Reset V alue Bit 7: POE5, PCA0 PWM5 main channel (PWM5O) output control. 0: Disable PWM5O output on port pin. 1: Enable PWM5O output on port pin. Default is enabled.
  • Page 109 CMT2380F17 Bit 1~0: S1PS1~0, Serial Port 1 pin Selection [1:0]. S1PS1, S1PS0 RxD1 TxD1 P1.0 P1.1 P6.0 P6.1 P4.4 P4.5 P3.4 P3.5 www.cmostek.com Rev0.1 | 109/347...
  • Page 110 CMT2380F17  AUXR10:Auxiliary Register 10 SFR Page = 7 only SFR Address = 0xA4 Name SPIPS0 S0PS1 TWICF Reset V alue Bit 4: SPIPS0, SPI Port pin Selection 0. SPIPS0 MOSI MISO SPICLK P3.3 P1.5 P1.6 P1.7 P1.7 P3.5 P3.4 P3.3...
  • Page 111 CMT2380F17 INT2IS[1:0] Selected Port Pin of nINT2 P4.4 P3.0 P1.1 P1.6 www.cmostek.com Rev0.1 | 111/347...
  • Page 112: Interrupt

    CMT2380F17 15 Interrupt The CMT2380F17 has 16 interrupt sources with a four-level interrupt structure. There are several SFRs associated with the four-level interrupt. They are the IE, IP0L, IP0H, EIE1, EIP1L, EIP1H, EIE2, EIP2L, EIP2H and XICON. The IP0H (Interrupt Priority 0 High), EIP1H (Extended Interrupt Priority 1 High) and EIP2H (Extended Interrupt Priority 2 High) registers make the four-level interrupt structure possible.
  • Page 113 CMT2380F17 Highest Priority IP0L,IP0H,EIP1L,EI Level Interrupt Global Enable P1H,EIP2L,EIP2H (IE.EA) Registers Interrupt Polling Sequence TCON.IT0 IE.EX0 INT0ET IE.ET0 TCON.TF0 TCON.IT1 IE.EX1 INT1ET IE.ET1 TCON.TF1 S0CON.RI0 IE.ES0 S0CON.TI0 TCON.TF2 IE.ET2 TCON.EXF2 XICON.IT2 XICON.EX2 INT2ET EIE1.ESPI SPSTAT.SPIF EIE1.EADC ADCON0.ADCI EIE1.EPCA PCA0 Interrupt Flags EIE1.ESF...
  • Page 114: Interrupt Source

    CMT2380F17 15.2 Interrupt Source Table15-2. Interrupt Source Flag Source Name Request Bits Bit Location External Interrupt 0,nINT0 TCON.1 Timer 0 TCON.5 External Interrupt 1,nINT1 TCON.3 Timer 1 TCON.7 S0CON.0 Serial Port 0 RI0, TI0 S0CON.1 TF2, EXF2, T2CON.7 (TF2L) Timer 2 T2CON.6...
  • Page 115 CMT2380F17 The Timer0 and Timer1 interrupts are generated by TF0 and TF1, which are set by a rollover in their respective Timer/Counter registers in most cases. When a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to.
  • Page 116 CMT2380F17 PCON1.WDTF SFIE.WDTFIE System Flag PCON1.BOF0 SFIE.BOF0IE Interrupt PCON1.BOF1 SFIE.BOF1IE PCON1.RTCF SFIE.RTCFIE EIE1.ESF PCON1.MCDF SFIE.MCDFIE S0CON.TI0 S0CFG.UTIE AUXR2.STAF AUXR2.STOF SFIE.SIDFIE Figure 15-2. System flag interrupt configuration The keypad interrupt is generated by KBCON.KBIF, which is set by Keypad module meets the input pattern.
  • Page 117: Interrupt Enable

    EDMA IE.6 There are 16 interrupt sources available in CMT2380F17. Each of these interrupt sources can be individually enabled or disabled by setting or clearing an interrupt enable bit in the registers IE, EIE1, EIE2 and XICON. IE also contains a global disable bit, EA, which can be cleared to disable all interrupts at once. If EA is set to ‘1’, the interrupts are individually enabled or disabled by their corresponding enable bits.
  • Page 118: Interrupt Process

    CMT2380F17 same priority level and the interrupt vector address. 15.5 Interrupt Process Each interrupt flag is sampled at every system clock cycle. The samples are polled during the next system clock. If one of the flags was in a set condition at first cycle, the second cycle (polling cycle) will find it and the interrupt system will generate an hardware LCALL to the appropriate service routine as long as it is not blocked by any of the following conditions.
  • Page 119: Nintx Input Source Selection And Input Filter (X=0~2)

    CMT2380F17 15.6 nINTx Input Source Selection and input filter (x=0~2) The CMT2380F17 provides flexible nINT0, nINT1 and nINT2 source selection to share the port pin inputs… Figure 15-2. Configuration of nINT0~2 Port Pin Selection www.cmostek.com Rev0.1 | 119/347...
  • Page 120: Interrupt Register

    CMT2380F17 15.7 Interrupt Register  TCON:Timer/Counter Control Register SFR Page = 0~F SFR Address = 0x88 Name Reset V alue Bit 3: IE1, Interrupt 1 (nINT1) Edge flag. 0: Cleared when interrupt processed on if transition-activated. 1: Set by hardware when external interrupt 1 (nINT1) edge is detected (transmitted or level-activated).
  • Page 121 CMT2380F17 Bit 7: EA, All interrupts enable register. 0: Global disables all interrupts. 1: Global enables all interrupts. Bit 6: EDMA, DMA group interrupt enable register. 0: Disable DMA group interrupt. 1: Enable DMA group interrupt. Bit 5: ET2, Timer 2 interrupt enable register. 0: Disable Timer 2 interrupt.
  • Page 122 CMT2380F17  AUXR0: Auxiliary Register 0 SFR Page = 0~F SFR Address = 0xA1 Name P60OC1 P60OC0 P60FD PBKF INT1H INT0H Reset V alue Bit 4: PBKF, PWM Break Flag. This bit is set by PWM break source enabled. If this flag is set, the enabled PWM channel 0~5 will be blocked and the output pins keep the original GPIO state.
  • Page 123 CMT2380F17 Bit 7: reserved. In case of writing IP0L, this bit must be set to 0 by software. Bit 6: PX2L, external interrupt 2 priority-L register. Bit 5: PT2L, Timer 2 interrupt priority-L register. Bit 4: PSL, Serial port interrupt priority-L register.
  • Page 124 CMT2380F17 1: Enable the interrupt when ACCON0.ADCI is set in ADC module. Bit 0: ESPI, Enable SPI Interrupt. 0: Disable the interrupt when SPSTAT.SPIF is set in SPI module. 1: Enable the interrupt when SPSTAT.SPIF is set in SPI module.。...
  • Page 125 CMT2380F17  EIE2:Extended Interrupt Enable 2 Register SFR Page = 0~F SFR Address = 0xA5 Name Reset V alue Bit 7~1: Reserved. Software must write “0” on these bits when EIE2 is written. Bit 0: ET3, Timer 3 interrupt enable register.
  • Page 126 CMT2380F17 Bit 7~6: INT1IS.1~0, nINT1 input port pin selection bits which function is defined with INT1IS.2 as following table. INT1IS[2:0] Selected Port Pin of nINT1 P3.3 P3.1 P3.5 P1.0 P6.1 P3.4 P1.5 P2.4 Bit 5~4: INT0IS.1~0, nINT0 input port pin selection bits which function is defined with INT0IS.2 as following table.
  • Page 127 CMT2380F17 Bit 6: INT0IS2, nINT0 input port pin selection bit which function is defined with INT0IS.1~0. Bit 5~4: INT2IS1~0, nINT2 input port pin selection bits which function is defined as following table.。 INT2IS[1:0] Selected Port Pin of nINT2 P4.4 P3.0 P1.1...
  • Page 128 CMT2380F17 Bit 1: BOF0IE, Enable BOF0 (PCON1.1) Interrupt. 0: Disable BOF0 interrupt. 1: Enable BOF0 interrupt. Bit 0: WDTFIE, Enable WDTF (PCON1.0) Interrupt. 0: Disable WDTF interrupt. 1: Enable WDTF interrupt.  PCON1:Power Control Register 1 SFR Page = 0~F & P...
  • Page 129 CMT2380F17 Bit 6: STOF, Stop Flag detection of STWI (SID). 0: Clear by firmware by writing “0” on it. 1: Set by hardware to indicate the STOP condition occurred on STWI bus. STOF might be held within MCU reset period, so needs to clear STOF in firmware initial.
  • Page 130: Timers/Counters

    CMT2380F17 16 Timers/Counters CMT2380F17 has four 16-bit Timers/Counters: Timer 0, Timer 1, Timer 2 and Timer 3. All of them can be configured as timers or event counters. In the “timer” function, the timer rate is prescaled by 12 clock cycle to increase register value. In other words, it is to count the standard C51 machine cycle.
  • Page 131 CMT2380F17 Figure 16-1. Timer 0 Mode 0 Structure Figure15-2. Timer 1 Mode 0 Structure www.cmostek.com Rev0.1 | 131/347...
  • Page 132: Timer 0/1 Mode 1

    CMT2380F17 16.1.2 Timer 0/1 Mode 1 Timer 0/1 in Mode1 is configured as a 16 bit timer or counter. The function of GATE, TxG1 and TRx is same as mode 0. Figure 16–3 and Figure 16–4 show the mode 1 structure of Timer 0 and Timer 1.
  • Page 133: Timer 0/1 Mode 2

    CMT2380F17 16.1.3 Timer 0/1 Mode 2 Mode 2 configures the timer register as an 8-bit counter (TLx) with automatic reload. Overflow from TLx not only set TFx, but also reload TLx with the content of THx, which is determined by software. The reload leaves THx unchanged.
  • Page 134: Timer 0/1 Mode 3

    CMT2380F17 16.1.4 Timer 0/1 Mode 3 Timer1 in Mode3 simply holds its count, the effect is the same as setting TR1 = 0. Timer0 in Mode 3 enables TL0 and TH0 as two separate 8-bit counters. TL0 uses the Timer0 control bits such like T0XL, T0X12, T0C/T, T0G1, T0GATE, TR0 and TF0.
  • Page 135 CMT2380F17 T0 Clock Frequency T0 Clock-out Frequency = 2 x (256 – TH0) Figure 16-8. Timer 0 clock out equation T1 Clock Frequency T1 Clock-out Frequency = 2 x (256 – TH1) Figure 16-9. Timer 0 clock out equation Note:...
  • Page 136: Timer 0/1 Register

    CMT2380F17 Figure 16-11. Timer 1 in Clock Output Mode How to Program Timer 0/1 in Clock-out Mode • Select Timer 0/1 clock source. • Determine the 8-bit reload value from the formula and enter it in the TH0/TH1 register. •...
  • Page 137 CMT2380F17 SFR Page = 0~F SFR Address = 0x89 Name T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 Reset V alue Bit 7: T1GATE, Gating control for Timer1. T1G1, T1GATE T1 Gate source Disable INT1 active TF3 active TI1 active Bit 6: T1C/T, Timer 1 clock source selector.
  • Page 138 CMT2380F17 Reset V alue  TL1:Timer 1 High byte Register SFR Page = 0~F SFR Address = 0x8B Name TL1[7:0] Reset V alue www.cmostek.com Rev0.1 | 138/347...
  • Page 139 CMT2380F17  TH1:Timer 1 High byte Register SFR Page = 0~F SFR Address = 0x8D Name TH1[7:0] Reset V alue  AUXR2: Auxiliary Register 2 SFR Page = 0~F SFR Address = 0xA3 Name STAF STOF T1X12 T0X12 T1CKOE T0CKOE Reset V alue Bit 3: T1X12, Timer 1 clock source selection with T1C/T control.
  • Page 140 CMT2380F17  AUXR3: Auxiliary Register 3 SFR Page = 0 only SFR Address = 0xA4 Name T0PS1 T0PS0 BPOC1 BPOC0 S0PS0 TWIPS1 TWIPS0 T0XL Reset V alue Bit 7~6: T0PS1~0, Timer 0 Port pin Selection [1:0]. T0PS1~0 T0/T0CKO P3.4 P4.4 P2.2...
  • Page 141: Timer 2

    CMT2380F17 16.2 Timer 2 Timer 2 is a 16-bit Timer/Counter which can operate either as a timer or an event counter, as selected by C/T2 in T2CON register. Timer 2 has four operating modes: Capture, Auto-Reload (up or down counting), Baud Rate Generator and Programmable Clock-Out, which are selected by bits in the T2CON, T2MOD and T2MOD1 registers.
  • Page 142: Timer 2 Mode 1 (Auto-Reload With External Interrupt)

    CMT2380F17 16.2.2 Timer 2 Mode 1 (Auto-Reload with External Interrupt) Figure 16–13 shows Timer 2 Mode 1, which enables Timer 2 to count up automatically. In this mode there are two options selected by bit EXEN2 in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overflow.
  • Page 143: Timer 2 Mode 2 (Capture)

    CMT2380F17 16.2.3 Timer 2 Mode 2 (Capture) Figure 16–14 shows the capture mode there are two options selected by bit EXEN2 in T2CON. If EXEN2=0, Timer 2 is a 16-bit timer or counter which, upon overflow, sets bit TF2 (Timer 2 overflow flag). This bit can then be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IE register).
  • Page 144: Timer 2 Mode 3 (Capture With Auto-Zero)

    CMT2380F17 16.2.4 Timer 2 Mode 3 (Capture with Auto-Zero) Timer 2 Mode 3 is the similar function with Timer 2 Mode 2. There is one difference that the T2EXES, EXF2 event set signal, not only is the capture source of Timer 2 but also clears the content of TL2 and TH2 to 0x0000H.
  • Page 145: Split Timer 2 Mode 0 (Ar And Ex. Int)

    CMT2380F17 16.2.5 Split Timer 2 Mode 0 (AR and Ex. INT) When T2SPL is set in this mode, Timer 2 operates as two 8-bit timers (TH2 and TL2). Both 8-bit timers operate in up-counter as shown in Figure 16–16. TH2 holds the reload value for RCAP2H and keep the same 8 clock source inputs selection as 16-bit mode.
  • Page 146: Split Timer 2 Mode 1 (Ar With Ex. Int)

    CMT2380F17 16.2.6 Split Timer 2 Mode 1 (AR with Ex. INT) When T2SPL is set in this mode, Timer 2 is split to two 8-bit timers as shown in Figure 16–17. It is similar function as Timer 2 Mode 1 and keeps the same interrupt scheme in Split Timer 2 Mode 0.
  • Page 147: Split Timer 2 Mode 2 (Capture)

    CMT2380F17 16.2.7 Split Timer 2 Mode 2 (Capture) When T2SPL is set in this mode, Timer 2 is split to two 8-bit timers as shown in Figure 16–18. It is similar function as Timer 2 Mode 2 and keeps the same interrupt scheme in Split Timer 2.
  • Page 148: Split Timer 2 Mode 3 (Capture With Auto-Zero)

    CMT2380F17 16.2.8 Split Timer 2 Mode 3 (Capture with Auto-Zero) When T2SPL is set in this mode, Timer 2 is split to two 8-bit timers as shown in Figure 16–19. It is similar function as Timer 2 Mode 3 and keeps the same interrupt scheme in Split Timer 2 Mode 0.
  • Page 149: Split Timer 2 Mode 4 (8-Bit Pwm Mode)

    CMT2380F17 16.2.9 Split Timer 2 Mode 4 (8-bit PWM Mode) In this mode, Timer 2 is an 8-bit PWM mode as shown in Figure 16–20. TH2 and RCAP2H are combined to an 8-bit auto-reload counter. Software configures these two registers to decide the PWM cycle time. TL2 is the PWM compare register to generate PWM waveform.
  • Page 150 CMT2380F17 rate generator, T2EX can be used as an additional external interrupt, if needed. When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2 and TL2. As a baud rate generator, Timer 2 is incremented at 1/2 the system clock or asynchronously from pin T2; under these conditions, a read or write of TH2 or TL2 may not be accurate.
  • Page 151: Timer 2 Programmable Clock Output

    CMT2380F17 Figure 16-22. Split Timer 2 in Baud-Rate Generator Mode 16.2.11 Timer 2 Programmable Clock Output Timer 2 has a Clock-Out Mode (while CP/RL2=0 & T2OE=1). In this mode, Timer 2 operates as a programmable clock generator with 50% duty-cycle. The generated clocks come out on P1.0. The input clock (SYSCLK/2 or SYSCLK) increments the 16-bit timer (TH2, TL2).
  • Page 152 CMT2380F17 frequency range from 91.5Hz to 6MHz. Figure 16-24. Timer 2 in Clock-Out Mode Timer 2 in Clock-Out Mode • Select Timer 2 clock source. • Determine the 16-bit reload value from the formula and enter it in the RCAP2H and RCAP2L registers.
  • Page 153: Timer 2 Register

    CMT2380F17 Figure 15-26. Split Timer 2 in Clock-Out Mode How to Program Split Timer 2 in Clock-out Mode • Select TL2 clock source. • Determine the 8-bit reload value from the formula and enter it in the RCAP2L register. Enter the same reload value as the initial value in the TL2 register.
  • Page 154 CMT2380F17 TL2IS (T2MOD1.5) must be cleared to enable access to the TCLK bit. Bit 4: TCLK, Transmit clock flag. 0: Causes Timer 1 overflows to be used for the transmit clock. 1: Causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3.
  • Page 155 CMT2380F17 ignore positive transition events at T2EX pin. 1: Allows a capture or reload to occur as a result of a 0-to1 transition on T2EX pin if Timer 2 is not being used to clock the serial port 0. If Timer 2 is configured to clock the serial port 0, the T2EX remains the external transition detection and reports on EXF2 flag with Timer 2 interrupt.
  • Page 156 CMT2380F17  TL2:Timer 2 Low byte Register SFR Page = 0 Only SFR Address = 0xCC Name TL2[7:0] Reset V alue  TH2:Timer 2 High byte Register SFR Page = 0 Only SFR Address = 0xCD Name TH2[7:0] Reset V alue ...
  • Page 157: Timer 3

    CMT2380F17 16.3 Timer 3 Timer 3 is a 16-bit Timer/Counter which can operate either as a timer or an event counter, as selected by C/T3 in T3CON register. Timer 3 has four operating modes: Capture, Auto-Reload (up or down counting) and Programmable Clock-Out, which are selected by bits in the T3CON, T3MOD and T3MOD1 registers.
  • Page 158: Timer 3 Mode 2 (Capture)

    CMT2380F17 Figure 16-28. Timer 3 Mode 1 Structure (Auto-Reload with External Interrupt Mode) 16.3.3 Timer 3 Mode 2 (Capture) Figure 16–29 shows the capture mode there are two options selected by bit EXEN3 in T3CON. If EXEN3=0, Timer 3 is a 16-bit timer or counter which, upon overflow, sets bit TF3 (Timer 3 overflow flag). This bit can then be used to generate an interrupt (by enabling the Timer 3 interrupt bit in the EIE2 register).
  • Page 159: Timer 3 Mode 3 (Capture And Auto-Zero)

    CMT2380F17 16.3.4 Timer 3 Mode 3 (Capture and Auto-Zero) Timer 3 Mode 3 is the similar function with Timer 3 Mode 2. There is one difference that the T3EXES, EXF3 event set signal, not only is the capture source of Timer 3 but also clears the content of TL3 and TH3 to 0x0000H.
  • Page 160: Split Timer 3 Mode 1 (Auto-Reload With External Interrupt)

    CMT2380F17 Figure 16-31. Split Timer 3 Mode 0 Structure (AR and Ex. INT). 16.3.6 Split Timer 3 Mode 1 (Auto-Reload with External Interrupt) When T3SPL is set in this mode, Timer 3 is split to two 8-bit timers as shown in Figure 16–32. It is similar function as Timer 3 Mode 1 and keeps the same interrupt scheme in Split Timer 3 Mode 0.
  • Page 161 CMT2380F17 Figure 16-32. Split Timer 3 Mode 1 Structure (AR with Ex. INT) www.cmostek.com Rev0.1 | 161/347...
  • Page 162: Split Timer 3 Mode 2 (Capture)

    CMT2380F17 16.3.7 Split Timer 3 Mode 2 (Capture) When T3SPL is set in this mode, Timer 3 is split to two 8-bit timers as shown in Figure 16–33. It is similar function as Timer 3 Mode 2 and keeps the same interrupt scheme in Split Timer 3 Mode 0.
  • Page 163: Split Timer 3 Mode 3 (Capture With Auto-Zero)

    CMT2380F17 16.3.8 Split Timer 3 Mode 3 (Capture with Auto-Zero) When T3SPL is set in this mode, Timer 3 is split to two 8-bit timers as shown in Figure 16–34. It is similar function as Timer 3 Mode 3 and keeps the same interrupt scheme in Split Timer 3 Mode 0.
  • Page 164: Split Timer 3 Mode 4 (8-Bit Pwm Mode)

    CMT2380F17 16.3.9 Split Timer 3 Mode 4 (8-bit PWM Mode) In this mode, Timer 3 is an 8-bit PWM mode as shown in Figure 16–35. TH3 and RCAP3H are combined to an 8-bit auto-reload counter. Software configures these two registers to decide the PWM cycle time. TL3 is the PWM compare register to generate PWM waveform.
  • Page 165 CMT2380F17 (2) For SYSCLK=12MHz and select SYSCLK/12 as Timer 3 clock source, Timer 3 has a programmable output frequency range from 45.7Hz to 3MHz. (3) For SYSCLK=12MHz and select SYSCLK as Timer 3 clock source, Timer 3 has a programmable output frequency range from 91.5Hz to 6MHz.
  • Page 166: Timer 3 Register

    CMT2380F17 Figure 16-39. Split Timer 3 in Clock-Out Mode How to Program Split Timer 3 in Clock-out Mode • Select TL3 clock source. • Determine the 8-bit reload value from the formula and enter it in the RCAP3L register. •...
  • Page 167 CMT2380F17 is configured to mode 0 which does no behave capture or reload function, the Timer 3 external input remains the external transition detection and reports on EXF3 flag with Timer 3 interrupt. Bit 2: TR3, Timer 3 Run control bit. If in Timer 3 split mode, it only controls the TH3.
  • Page 168 CMT2380F17 Bit 0: T3MS0, Timer 3 mode select bit 0. Timer 3 Mode Selection T3MS1, CP/RL3, T3MS0 Mode 0: Auto-Reload and External Interrupt 0 0 0 Mode 1: Auto-Reload with External Interrupt 0 0 1 0 1 0 Mode 2: Capture mode...
  • Page 169 CMT2380F17 Name TH2[7:0] Reset V alue  RCAP3L:Timer 3 Capture Low byte Register SFR Page = 1 Only SFR Address = 0xCA Name RCAP2[7:0] Reset V alue  RCAP3H:Timer 3 Capture High byte Register SFR Page = 1 Only SFR Address = 0xCB...
  • Page 170: Timer Global Control

    CMT2380F17 16.4 Timer Global Control When the applications are asking all timers work together in sync mode, it can set the registers to Start, Reload and Stop the timers. 16.4.1 Global Enable for all Timer Run When the applications are asking all timers work together in sync mode, just need to set the TRxE or TRxLE in TREN0 to start the timer at the same time.
  • Page 171: Global Control For All Timer Reload

    CMT2380F17 16.4.2 Global Control for all Timer Reload  TRLC0:Timer Reload Control Register 0 SFR Page = 2 Only SFR Address = 0x95 RESET= 0000-0000 Name TL3RLC TL2RLC T3RLC T2RLC T1RLC T0RLC Reset V alue Bit 7: Reserved. Software must write “0” on this bit when TRLC0 is written.
  • Page 172: Global Control For All Timer Stop

    CMT2380F17 16.4.3 Global Control for all Timer Stop  TSPC0:Timer Stop Control Register 0 SFR Page = 3 Only SFR Address = 0x95 RESET= 0000-0000 Name TL3SC TL2SC T3SC T2SC T1SC T0SC Reset V alue Bit 7: Reserved. Software must write “0” on this bit when TSPC0 is written.
  • Page 173: Programmable Counter Array (Pca0)

    CMT2380F17 17 Programmable Counter Array (PCA0) The CMT2380F17 is equipped with a Programmable Counter Array (PCA0), which provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. 17.1 PCA Overview The PCA consists of a dedicated timer/counter which serves as the time base for an array of Six capture/compare/PWM modules and Two compare/PWM modules.
  • Page 174 CMT2380F17 and low bytes of the count values), CHRL, CLRL (the high and low bytes reload registers), as shown in Figure 17–2. CHRL and CLRL are reloaded to CH and CL at each time overflow on {CH+CL} counter which can change the PCA cycle time for variable PWM resolution, such as 7-bit or 9-bit PWM.
  • Page 175 CMT2380F17  CMOD:PCA Counter Mode Register SFR Page = 0 Only SFR Address = 0xD9 Name CIDL BME4 BME2 BME0 CPS2 CPS1 CPS0 Reset V alue Bit 7: CIDL, PCA counter Idle control. 0: Lets the PCA counter continue functioning during Idle mode. 1: Lets the PCA counter be gated off during Idle mode.
  • Page 176 CMT2380F17 SFR Page = 0 only SFR Address = 0xD8 Name CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 Reset V alue Bit 7: CF, PCA Counter Overflow flag. 0: Only be cleared by software. 1: Set by hardware when the counter rolls over. CF flag can generate an interrupt if bit ECF in CMOD is set.
  • Page 177 CMT2380F17 Figure 17-3. PCA Interrupt System www.cmostek.com Rev0.1 | 177/347...
  • Page 178 CMT2380F17  PCAPWMn:PWM Mode Auxiliary Register, n=0~7 SFR Page = 0 only for n= 0~1 (n=2~5 for all page) SFR Page = 1 only for n= 6~7 SFR Address = 0xF2~0xF7 Name PnRS1 PnRS0 CCFn PnINV ECAPnH ECAPnL Reset V alue Bit 3: CCFn, only CCF6 and CCF7 are valid for the interrupt flag in module 6 and module 7.
  • Page 179: Compare/Capture Modules

    CMT2380F17  CLRL:PCA CL Reload Register SFR Page = 0 ~ F SFR Address = 0xCE Name CLRL[7:0] Reset V alue Bit 7~0: CLRL, reload value of CL. 17.3 Compare/Capture Modules Each of the compare/capture module 0~7 has a mode register called CCAPMn (n = 0,1,2,3,4,5,6 or 7) to select which function it will perform.
  • Page 180 CMT2380F17 compare/capture flag CCFn in the CCON register to generate an interrupt. Note: The bits CAPNn (CCAPMn.4) and CAPPn (CCAPMn.5) determine the edge on which a capture input will be active. If both bits are set, both edges will be enabled and a capture will occur for either transition.
  • Page 181 CMT2380F17 When a module is used in the PWM mode, in addition to the above two registers, an extended register PCAPWMn is used to improve the range of the duty cycle of the output. The improved range of the duty cycle starts from 0%, up to 100%, with a step of 1/256. About 10/12/16 bit PWM please reference 17.4.6...
  • Page 182: Operation Modes Of The Pca

    CMT2380F17  CCAPnL:PCA Module n Capture Low Register, n=0~7 SFR Page = 0 only for n= 0~1 (n=2~5 for all page) SFR Page = 1 only for n= 6~7 SFR Address = 0xEA~0xEF Name CCAPnL[7:0] Reset V alue  PCAPWMn:PWM Mode Auxiliary Register, n=0~7...
  • Page 183: Capture Mode

    CMT2380F17 CEXn 16-bit capture by a transition on CEXn 16-bit Software Timer (Compare) 16-bit High Speed Output (HSO) Pulse Width Modulator (PWM) Compare Output on PWM match case (COPM) FIFO Data Mode Note: PCA Module 6 and module 7 don’t support the capture mode.
  • Page 184 CMT2380F17 PCA Interrupt CCON CCAPnH CCAPnL n = 1, 3, 5 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 (To CCFn) CCAPnH CCAPnL n = 0, 2, 4 CEXn Capture n = 0, 2, 4 PCA Timer/Counter CCAPMn overflow ECOMn CAPPn CAPNn...
  • Page 185: 16-Bit Software Timer Mode (Compare Mode)

    CMT2380F17 17.4.3 16-bit Software Timer Mode (Compare mode) The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the module’s CCAPMn register. The PCA timer will be compared to the module’s capture registers, and when a match occurs an interrupt will occur if the CCFn and the ECCFn bits for the module are both set.
  • Page 186: Un-Buffered 10/12/16-Bit Pwm Mode

    CMT2380F17 All of the PCA modules can be used as PWM outputs. The frequency of the output depends on the clock source for the PCA timer. All of the modules will have the same frequency of output because they all share the PCA timer.
  • Page 187: Buffered 10/12/16-Bit Pwm Mode

    CMT2380F17 Figure 17-10. PCA Un-buffered10/12/16-bit PWM Mode 17.4.7 Buffered 10/12/16-bit PWM Mode To use 10/12/16-bit PWM mode might cause unexpected duty cycle when change the duty cycle setting by writing data into CCAPnH and CCAPnL, because the 8 bit CPU can only write one byte at a time. To finish fully setting it will take two write cycles, and the comparator will output unexpected duty cycle when the first byte have been written.
  • Page 188: Copm Mode

    CMT2380F17 17.4.8 COPM Mode Compare Output on PWM Match mode is similar to High Speed Output Mode, but it uses PCA0 PWM comparators instead of fixed 16-bit comparators. It gives more flexibility to the applications. For example, if it uses 8-Bit PWM for the PCA0 comparator, the output toggles frequency can higher than High Speed Output Mode.
  • Page 189: Buffered Copm Mode

    CMT2380F17 17.4.9 Buffered COPM Mode If the applications need to have any phase control of the PWM signals, it needs to set the PCA0 modules in buffered COPM mode. One pair of the PCA0 module (n=0&1 / 2&3 / 4&5) can program the time delay of the two edges of one cycle of the PWM signal.
  • Page 190: Fifo Data Mode

    CMT2380F17 17.4.10 FIFO Data Mode In this mode the user can set the CCAPnL, CCAPnH, CCAP(n+1)L and CCAP(n+1)H as a buffer chain. After all these buffers are set, it can change the duty sequentially trigger by T0OF, T1OF, T3OF or S0TOF.
  • Page 191 CMT2380F17 resolution and different phase delay can operate concurrently. Figure 17-15. PWM Waveform with Dead-Time Control  CCAPMn:PCA Module Compare/Capture Register, n=0~5 SFR Page = 0 only for n= 0~1 (n=2~5 for all page) SFR Address = 0xDA~0xDF Name DTEn...
  • Page 192 CMT2380F17 Bit 7~6: DTPS1~0, Clock Pre-Scaler of Dead-Time counter. Pre-Scaler DTPS[1:0] Selection SYSCLK SYSCLK/2 SYSCLK/4 SYSCLK/8 Bit 5~0: DT5~0, Dead-Time period control bits. DT[5:0] Dead-Time Period Dead-Time Disabled 000000 Pre-Scaler Clock X 1 000001 Pre-Scaler Clock X 2 000010 Pre-Scaler Clock X 3 000011 ……...
  • Page 193 CMT2380F17 1: Cycle-by-cycle Mode. Figure 17-17. Latch Mode Waveform of PWM Break control Figure 17-18. Cycle-by-Cycle Mode Waveform of PWM Break control Bit 4~3: PBKE1.1~0, PWM Break Enable 1 selection. This function is only active on CEXn output mode (n=0~5).
  • Page 194: Pca Module Output Control

    CMT2380F17 Figure 17-19. PCA PWM Break control source  AUXR0:Auxiliary Register 0 SFR Page = 0~F SFR Address = 0xA1 Name P60OC1 P60OC0 P60FD PBKF INT1H INT0H Reset V alue Bit 4: PBKF, PWM Break Flag. This bit is set by PWM break source enabled. If this flag is set, the enabled PWM channel 0~5 will be blocked and the output pins keep the original GPIO state.
  • Page 195 CMT2380F17 Figure 17-20. PCA Module output control  PAOE:PWM Additional Output Enable Register SFR Page = 0~F SFR Address = 0xF1 Name POE3 POE2B POE2A POE2 POE1 POE0B POE0A POE0 www.cmostek.com Rev0.1 | 195/347...
  • Page 196 CMT2380F17 Reset V alue Bit 7: POE3, PCA0 PWM3 main channel (PWM3O) output control. 0: Disable PWM3O output on port pin. 1: Enable PWM3O output on port pin. Default is enabled. Bit 6: POE2B, PCA0 PWM2 3rd channel (PWM2B) output control.
  • Page 197 CMT2380F17 Name C0IC4S0 C0IC2S0 C0PPS1 C0PPS0 C0PS0 ECIPS0 C0COPS Reset V alue Bit 7: C0IC4S0, PCA0 Input Channel 4 input port pin Selection. C0IC4S0 CEX4 input CEX4 Port Pin T2EXI Bit 6: C0IC2S0, PCA0 Input Channel 2 input port pin Selection.
  • Page 198: Variable Resolution On Central Aligned Pwm

    CMT2380F17 Bit 6: POE6, PCA0 PWM6 main channel (PWM6O) output control. 0: Disable PWM6O output on port pin. 1: Enable PWM6O output on port pin. Default is enabled. Bit 5: C0PPS2, {PWM6, PWM7} Port pin Selection 2. C0PPS2 PWM6 PWM7 P6.0...
  • Page 199 CMT2380F17  AUXR11:Auxiliary Register 11 SFR Page = 8 only SFR Address = 0xA4 P30AM C0M0 C0OFS Name Reset V alue Bit 1: C0M0, PCA0 Mode control 0. 0: Not support variable resolution on central aligned PWM. 1: Enable PCA0 variable resolution central aligned PWM. To enable this function, the PCAE also needs to be set.
  • Page 200: Serial Port 0 (Uart0)

    CMT2380F17 18 Serial Port 0 (UART0) The serial port 0 of CMT2380F17 support full-duplex transmission, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. However, if the first byte still hasn’t been read by the time reception of the second byte is complete, one of the bytes will be lost.
  • Page 201: Serial Port 0 Mode 0

    CMT2380F17 In addition to the standard operation, the UART0 can perform framing error detection by looking for missing stop bits, and automatic address recognition.。 18.1 Serial Port 0 Mode 0 Serial data enters and exits through RXD0. TXD0 outputs the shift clock. 8 bits are transmitted/received: 8 data bits (LSB first).
  • Page 202: Serial Port 0 Mode 1

    CMT2380F17 Figure 18-4. Mode 0 Transmission Waveform Figure 18-5. Mode 0 Reception Waveform 18.2 Serial Port 0 Mode 1 10 bits are transmitted through TXD0, or received through RXD0: a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB80 in S0CON. The baud rate is determined by the Timer 1 or Timer 2 overflow rate.
  • Page 203: Serial Port 0 Mode 2 And Mode 3

    CMT2380F17 Mode 2 Mode 1, 3 clock source clock source Timer 2 Timer 1 80C51 Internal BUS SYSCLK/2 Overflow Overflow Write S0BUF SM00 “0” “1” “0” “1” TXD0 TXBUF SM10 SMOD1 TB80 SMOD2 “1” “0” RXD0 RXBUF TCLK TX Clock...
  • Page 204: Frame Error Detection

    CMT2380F17 18.4 Frame Error Detection When used for framing error detection, the UART0 looks for missing stop bits in the communication. A missing stop bit will set the FE bit in the S0CON register. The FE bit shares the S0CON.7 bit with SM00 and the function of S0CON.7 is determined by SMOD0 bit (PCON.6).
  • Page 205 CMT2380F17 Automatic Address Recognition is a feature which allows the UART0 to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of firmware overhead by eliminating the need for the firmware to examine every serial address which passes by the serial port.
  • Page 206: Baud Rate Setting

    CMT2380F17 address will be FF hexadecimal. Upon reset SADDR (SFR address 0xA9) and SADEN (SFR address 0xB9) are loaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the micro-controller to use standard 80C51 type UART drivers which do not make use of this feature.
  • Page 207: Baud Rate In Mode 2

    CMT2380F17 ; n=12, if URM0X3=0 SYSCLK Mode 0 Baud Rate = ; n=4, if URM0X3=1 Note: If URM0X3=0, the baud rate formula is as same as standard 8051. 18.7.3 Baud Rate in Mode 2 When URM0X3 = 0, SMOD1 (SMOD2 X 2)
  • Page 208: Using Timer 1 As The Baud Rate Generator

    CMT2380F17 Table 18-1. SMOD2 application criteria in Mode 2 Recommended Max. Baud Rate Note SMOD2 SMOD1 Receive Error (%)  3% Default Baud Rate Standard function  3% Double Baud Rate Standard function  2% Double Baud Rate X2 Enhanced function ...
  • Page 209 CMT2380F17 Recommended Max. SMOD2 SMOD1 Baud Rate Note Receive Error (%)  3% Default Baud Rate Standard function  3% Double Baud Rate Standard function  2% Double Baud Rate X2 Enhanced function  1% Double Baud Rate X4 Enhanced function Note: When Timer 1 in Double Baud Rate x4 (SMOD1=1 &...
  • Page 210 CMT2380F17 Table 18-7. Timer 1 Generated Commonly Used Baud Rates @ FSYSCLK=22.1184MHz TH1, the Reload Value Baud Rate T1X12=0 & SMOD2=0 T1X12=1 & SMOD2=0 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 1200 0.0% 2400 0.0% 0.0% 4800 0.0% 0.0% 9600 0.0% 0.0%...
  • Page 211 CMT2380F17 TH1, the Reload Value T1X12=0 & SMOD2=0 T1X12=1 & SMOD2=0 Baud Rate SMOD=0 SMOD=1 Error SMOD=0 SMOD=1 Error 115200 Table 18-10. Timer 1 Generated High Baud Rates @ FSYSCLK=12.0MHz TH1, the Reload Value Baud Rate T1X12=0 & SMOD2=1 T1X12=1 & SMOD2=1...
  • Page 212 CMT2380F17 Table 18-13. Timer 1 Generated Commonly Used Baud Rates @ FSYSCLK=29.4912MHz TH1, the Reload Value Baud Rate T1X12=0 & SMOD2=0 T1X12=1 & SMOD2=0 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 0.0% 1200 0.0% 2400 0.0% 0.0% 4800 0.0% 0.0% 9600 0.0%...
  • Page 213 CMT2380F17 TH1, the Reload Value T1X12=0 & SMOD2=0 T1X12=1 & SMOD2=0 Baud Rate SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 0.0% 460.8K 0.0% 921.6K 1.8432M 0.0% 2.7648M Table 18-16. Timer 1 Generated High Baud Rates @ FSYSCLK=44.2368MHz TH1, the Reload Value Baud Rate T1X12=0 &...
  • Page 214 CMT2380F17 TH1, the Reload Value T1X12=0 & SMOD2=0 T1X12=1 & SMOD2=0 Baud Rate SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 1200 0.16% 2400 0.16% 4800 0.16% 9600 0.16% 0.16% 14400 2.12% 0.16% 19200 0.16% 0.16% 28800 0.16% 38400 0.16% 57600 0.16% 115200 0.16%...
  • Page 215: Using Timer 2 As The Baud Rate Generator

    CMT2380F17 18.7.4.2 Using Timer 2 as the Baud Rate Generator When Timer 2 is used as the baud rate generator (either TCLK or RCLK in T2CON is ‘1’), the baud rate is as follows. SMOD2 X (SMOD1 + 1) SYSCLK Mode 1, 3 Baud Rate = ;...
  • Page 216 CMT2380F17 Table 18-23. Timer 2 Generated High Baud Rates @ FSYSCLK=11.0592MHz [RCAP2H, RCAP2L] ,the Reload Value Baud Rate T2X12=0 & SMOD2=1 T2X12=1 & SMOD2=1 SMOD1=0 SMOD1=1 Error SMOD=0 SMOD=1 Error 230.4K 65533 65530 0.0% 65530 65524 0.0% 460.8K 65533 0.0%...
  • Page 217 CMT2380F17 Table 18-26. Timer 2 Generated Commonly Used Baud Rates @ FSYSCLK=12.0MHz [RCAP2H, RCAP2L] ,the Reload Value Baud Rate T2X12=0 & SMOD2=0 T2X12=1 & SMOD2=0 SMOD=0 SMOD=1 Error SMOD=0 SMOD=1 Error 1200 65224 65224 0.16% 64912 64912 0.16% 2400 65380 65380 0.16%...
  • Page 218 CMT2380F17 Table 18-29. Timer 2 Generated High Baud Rates @ FSYSCLK=24.0MHz [RCAP2H, RCAP2L] ,the Reload Value Baud Rate T2X12=0 & SMOD2=1 T2X12=1 & SMOD2=1 SMOD1=0 SMOD1=1 Error SMOD=0 SMOD=1 Error 230.4K 65523 0.16% 65523 65510 0.16% 460.8K 65523 0.16% 691.2K 921.6K...
  • Page 219 CMT2380F17 Table 18-32. Timer 2 Generated Commonly Used Baud Rates @ FSYSCLK=44.2368MHz [RCAP2H, RCAP2L], the Reload Value Baud Rate T2X12=0 & SMOD2=0 T2X12=1 & SMOD2=0 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 1200 64384 64384 0.0% 63232 63232 0.0% 2400 64960 64960 0.0%...
  • Page 220: Using S0 Baud Rate Timer As The Baud Rate Generator (S0Brg)

    18.7.4.3 Using S0 Baud Rate Timer as the Baud Rate Generator (S0BRG) The S0 of CMT2380F17 has embedded a dedicated baud rate generator (S0BRG), which detailed function is described in Section “18.10.2 Independent Baud Rate Generator S0BRG for S0”. When S0BRG is used as the baud rate generator of S0, the baud rate is as follows.
  • Page 221: Using S1 Baud Rate Timer As The Baud Rate Generator

    18.8 Serial Port 0 Mode 4 (SPI Master) The Serial Port 0 of CMT2380F17 is embedded an additional Mode 4 to support SPI master engine. The Mode 4 is selected by SM30, SM00 and SM10. Table 18–38 shows the serial port mode definition in MG82F6D17.
  • Page 222 CMT2380F17 MCU Serial Port n TXDn SPICLK RXDn MOSI Slave #1 SnMI MISO Port Pin 1 Mode 4 (Master) SPICLK MOSI Slave #2 MISO Port Pin 2 Figure 18-12. Serial Port 0 Mode 4, Single Master and Multiple Slaves configuration (n = 0) The SPI master satisfies the transfer with the full function SPI module of Megawin MG82/84 series MCU with CPOL, CPHA and DORD selection.
  • Page 223: Serial Port 0 Register

    CMT2380F17 Figure 18-13. Serial Port 0 Mode 4 transmission waveform (n = 0) 18.9 Serial Port 0 Register All the four operation modes of the serial port are the same as those of the standard 8051 except the baud rate setting. Three registers, PCON, AUXR2 and S0CFG, are related to the baud rate setting: ...
  • Page 224 CMT2380F17 0: Must be cleared by software. 1: Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM20).
  • Page 225 CMT2380F17 Bit 6: SMOD0, Frame Error select. 0: S0CON.7 is SM0 function. 1: S0CON.7 is FE function. Note that FE will be set after a frame error regardless of the state of SMOD0.  S0CFG:Serial Port 0 Configuration Register SFR Page...
  • Page 226: Serial Port 0 Enhance Function

    CMT2380F17 Bit 3: T1X12, Timer 1 clock source selector while C/T=0. 0: Clear to select SYSCLK/12. 1: Set to select SYSCLK as the clock source. If set, the UART0 baud rate by Timer 1 in Mode 1 and Mode 3 is 12 times than standard 8051 function.。...
  • Page 227 CMT2380F17 Bit 5: S0TCK, S0 control bit to select S0BRG overflow for UART0 transmit clock. 0: Cause Timer 1 or Timer 2 overflow to be used for the transmit clock. 1: Cause the S0 to use S0BRG overflow for it’s transmit clock and operating mode control.
  • Page 228: S0 Baud Rate Generator (S0Brg)

    CMT2380F17 18.10.1 S0 Baud Rate Generator (S0BRG) The CMT2380F17 has an embedded Baud Rate Generator to generate the clock for serial port 0 operation. It is constructed by an 8-bit up-counter, S0BRC, and an 8-bit reload register, S0BRT. The overflow (S0TOF) of S0BRC is the time base of UART0 serial engine in all operation modes and triggers the S0BRT content reloaded into S0BRC for the consecutive counting.
  • Page 229: S0 Enhanced Mode

    CMT2380F17 18.10.3 S0 Enhanced Mode SM30,SM00,SM10 S0RCK S0TCK Function Baud Rate Time Base Note shift SYSCLK/12 or register SYSCLK/4 (URM0X3=1) When SMOD1 & SMOD2 =1, 8-bit counter cannot be Full-1 or Timer 1 or Timer 2 overflow UART Full-2 (Ex. 254, 255, 65534,...
  • Page 230: S0 Acts As 8-Bit Timer Mode

    CMT2380F17 Bit 4: ATBR0, Auto Baud Rate on S0. 0: Auto cleared by hardware at the end of SYNC field. 1: Before SYNC field, set by software to perform auto baud rate adjustment on LIN bus SYNC field in slave RX mode.
  • Page 231: S0Brg Programmable Clock Output

    CMT2380F17 18.10.7 S0BRG Programmable Clock Output S0BRG has a clock output mode is shown in Figure 18–18. Figure 18–18. S0BRG Clock Output (S0BRG in 8-bit Timer Mode) Figure 18–19. S0BRG Clock Output (S0BRG for UART Mode)  AUXR6:Auxiliary Register 6...
  • Page 232: Serial Port 1 (Uart1)

    19.1 Serial Port 1 Baud Rate Generator (S1BRG) The CMT2380F17 has an embedded Baud Rate Generator to generate the UART clock for serial port 1 operation in mode 1 and mode 3. It is constructed by an 8-bit up-counter, S1BRC, and an 8-bit reload register, S1BRT.
  • Page 233: Baud Rate In Mode 2

    CMT2380F17 19.2.2 Baud Rate in Mode 2 When S1M0X3 = 0, When S1M0X3 = 1, Table 19–1. S1 Mode 2 Baud Rates @ FSYSCLK=11.0592MHz BaudRate S1M0X3 S1MOD1 Error  0.0% 172,800  0.0% 345,600  0.0% 57,600  0.0% 115,200 Table 19–2.
  • Page 234 CMT2380F17 57600 0.0% 0.0% 115200 0.0% 230400 0.0% Table 19–4. S1BRG Generated Commonly Used Baud Rates @ FSYSCLK=22.1184MHz S1BRT, Reload Value of S1BRG Baud Rate S1TX12 = 0 S1TX12 = 1 S1MOD1=0 S1MOD1=1 Error S1MOD1=0 S1MOD1=1 Error 1200 0.0% 2400 0.0%...
  • Page 235 CMT2380F17 9600 0.16% 0.16% 14400 0.16% 19200 0.16% 28800 0.16% 38400 0.16% 57600 0.16% 115200 0.16% Table 19–7. S1BRG Generated Commonly Used Baud Rates @ FSYSCLK=29.4912MHz S1BRT, Reload Value of S1BRG S1TX12 = 0 S1TX12 = 1 Baud Rate S1MOD1=0...
  • Page 236: Serial Port 1 Mode 4 (Spi Master)

    19.3 Serial Port 1 Mode 4 (SPI Master) The Serial Port of CMT2380F17 is embedded Mode 4 to support SPI master engine. The Mode 4 is selected by SM31, SM01 and SM11. Table 19–11 shows the serial port mode definition in MG82F6D17.。...
  • Page 237 CMT2380F17 8-bit UART variable 9-bit UART SYSCLK/64, /32 or /192, /96 9-bit UART variable SPI Master SYSCLK/12 or SYSCLK/4 Reserved variable Reserved Reserved Reserved variable S1M0X3 also controls the SPI transfer speed. If S1M0X3 = 1, the SPI clock frequency is SYSCLK/4.
  • Page 238: 8-Bit Timer Mode On S1Brg

    CMT2380F17 output register to “0” Clear TXD1 output register to “0” Clear TXD1 output register to “1” TXD1 output register to “1” TXD1 For bit order control (DORD) on SPI serial transfer, MG82F6D17 provides a control bit, S1DOR, to control the data bit order by software program. The default value of S1DOR is “1”, LSB first.
  • Page 239 CMT2380F17 Figure 19–5. 8-bit Timer Mode Configuration for S1BRG (S1TME=1) www.cmostek.com Rev0.1 | 239/347...
  • Page 240: 16-Bit Timer Mode On S1Brg

    CMT2380F17 19.5 16-Bit Timer Mode on S1BRG Figure 19–6. 16-Bit Timer Mode on S1BRG(S1TME=1) 19.6 S1BRT Programmable Clock Output When S1BRC overflows, the overflow flag, S1TOF, provides the toggle source for S1CKO and peripheral clock. The input clock (SYSCLK/12 or SYSCLK) increases the 8-bit timer, S1BRC. The timer repeatedly counts to overflow from a loaded value.
  • Page 241: How To Program 8-Bit S1Brg In Clock-Out Mode

    CMT2380F17 Figure 19–8. S1BRG Clock Output (S1BRG for UART Mode) How to Program 8-bit S1BRG in Clock-out Mode  Select S1CFG.S1TX12 bit and S1CON.SM21 bit to decide the S1BRG clock source.  Determine the 8-bit reload value from the formula and enter it in the S1BRT and S1BRC registers.
  • Page 242: S1 Baud Rate Generator For S0

    CMT2380F17 19.7 S1 Baud Rate Generator for S0 In the Mode 1 and Mode 3 operation of the UART0, the software can select Timer 1 as the Baud Rate Generator by clearing bits TCLK and RCLK in T2CON register. At this time, if URTS bit (S0CFG.7) is set, then Timer 1 overflow signal will be replaced by the overflow signal of the UART1 Baud Rate Generator (S1BRG).
  • Page 243 CMT2380F17 SPI Master SYSCLK/12 or SYSCLK/4 Reserved Reserved Reserved Reserved Reserved Reserved Bit 5: Serial port 1 mode bit 2. 0: Disable SM21 function. 1: Enable the automatic address recognition feature in Modes 2 and 3. If SM21=1, RI1 will not be set unless the received 9th data bit is 1, indicating an address, and the received byte is a given or Broadcast address.
  • Page 244 CMT2380F17  S1BUF:Serial port 1 Buffer Register SFR Page = 1 only SFR Address = 0x99 Name S1BUF[7:0] Reset V alue Bit 7~0: It is used as the buffer register in transmission and reception. S1BRT:Serial port 1 Baud Rate Timer Reload Register...
  • Page 245 CMT2380F17 the baud rate for S1 Mode 0 and Mode 4. S1 in mode 2: 0: Clear to select UART1 baud rate as SYSCLK/32 or /64. 1: Set to select UART1 baud rate as SYSCLK/96 or /192. Bit 5: S1DOR, Serial Port 1 data order control in all operating modes. If S1TME = 0: 0: The MSB of the data byte is transmitted first.
  • Page 246 CMT2380F17 SnMIPS S0MI S1MI P3.3 P4.7 www.cmostek.com Rev0.1 | 246/347...
  • Page 247: Serial Peripheral Interface (Spi)

    CMT2380F17 20 Serial Peripheral Interface (SPI) The CMT2380F17 provides a high-speed serial communication interface, the SPI interface. SPI is a full-duplex, high-speed and synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 24 Mbps can be supported in Master or 12MHz in Slave mode under a 48MHz system clock. It has a Transfer Completion Flag (SPIF), Write Collision Flag (WCOL) and Mode Fault flag (MODF) in the SPI status register (SPSTAT).
  • Page 248: Typical Spi Configurations

    CMT2380F17 1. See the AUXR8 in Section “4.3 Alternate Function Redirection”, for its alternate pin-out option. 2. Even if the SPI is configured as a master (MSTR=1), it can still be converted to slave mode by the logic low of nSS pin input (if SSIG=0). Should this happen, the SPIF bit (SPSTAT.7) will be set and SPEN will be cleared.
  • Page 249: Configuring The Spi

    CMT2380F17 SPICLK SPICLK MOSI MOSI Slave #1 MISO MISO Port Pin 1 Master SPICLK MISO Slave #2 MOSI Port Pin 2 Figure 20-4. SPI single master multiple slaves configuration 20.2 Configuring the SPI Table 20–1 shows configuration for the master/slave modes as well as usages and directions for the modes.
  • Page 250: Additional Considerations For A Slave

    CMT2380F17 20.2.1 Additional Considerations for a Slave When CPHA is 0, SSIG must be 0 and nSS pin must be negated and reasserted between each successive serial byte transfer. Note the SPDAT register cannot be written while nSS pin is active (low), and the operation is undefined if CPHA is 0 and SSIG is 1.
  • Page 251: Spi Clock Rate Select

    CMT2380F17 The SPI in CMT2380F17 is double buffered data both in the transmit direction and in the receive direction. New data for transmission cannot be written to the THR until the THR is empty. The read-only flag, THRF, indicates the THR is full or empty. The WCOL (SPSTAT.6) bit is set to indicate data collision when the data register is written during set THRF.
  • Page 252: Data Mode

    CMT2380F17 20.3 Data Mode Clock Phase Bit (CPHA) allows the user to set the edges for sampling and changing data. The Clock Polarity bit, CPOL, allows the user to set the clock polarity. The following figures show the different settings of Clock Phase Bit, CPHA.
  • Page 253 CMT2380F17 Figure 20-7. SPI Master Transfer Format with CPHA=0 Figure 20-8. SPI Master Transfer Format with CPHA=1 www.cmostek.com Rev0.1 | 253/347...
  • Page 254: Daisy-Chain Connection

    CMT2380F17 20.4 Daisy-Chain Connection If SPI0 is defined in slave mode, it can be connected in a daisy-chain configuration. The first slave output is connected to the second slave input, the second slave output is connected to the third slave input, and so on.
  • Page 255 CMT2380F17 Bit 3: CPOL, SPI clock polarity select 0: SPICLK is low when Idle. The leading edge of SPICLK is the rising edge and the trailing edge is the falling edge. 1: SPICLK is high when Idle. The leading edge of SPICLK is the falling edge and the trailing edge is the rising edge.
  • Page 256 CMT2380F17  SPSTAT: SPI Status Register SFR Page = 0~F SFR Address = 0x84 Name SPIF WCOL THRF SPIBSY MODF SPR2 Reset V alue Bit 7: SPIF, SPI transfer completion flag 0: The SPIF is cleared in software by writing “1” to this bit.
  • Page 257 CMT2380F17  SPDAT:SPI Data Register SFR Page = 0~F SFR Address = 0x86 Name SPDAT[7:0] Reset V alue SPDAT has two physical buffers for writing to and reading from during transmit and receive, respectively.  AUXR7: Auxiliary Register 7 SFR Page...
  • Page 258: Two Wire Serial Interface (Twi0/ I2C0)

    CMT2380F17 21 Two Wire serial Interface (TWI0/ I2C0) The Two-Wire serial Interface is a two-wire, bi-directional serial bus. It is ideally suited for typical microcontroller applications. The TWI/ I2C protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for clock (TWI0_SCL) and one for data (TWI0_SDA).
  • Page 259: Master Transmitter Mode

    CMT2380F17 1) Master/Transmitter mode; 2) Master/Receiver mode; 3) Slave/Transmitter mode; 4) Slave/Receiver mode. Bits STA, STO and AA in SICON decide the next action which the TWI hardware will take after SI is cleared by software. When the next action is completed, a new status code in SISTA will be updated and SI will be set by hardware in the same time.
  • Page 260: Master Receiver Mode

    CMT2380F17 21.1.2 Master Receiver Mode In the master receiver mode, a number of data bytes are received from a slave transmitter. SICON must be initialized as in the master transmitter mode. When the start condition has been transmitted, the interrupt service routine must load SIDAT with the 7-bit slave address and the data direction bit (SLA+R).
  • Page 261: Slave Receiver Mode

    CMT2380F17 and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate TWI/ I2C from the bus. 21.1.4 Slave Receiver Mode In the slave receiver mode, a number of data bytes are received from a master transmitter. Data transfer is initialized as in the slave transmitter mode.
  • Page 262: Using The Twi/ I2C

    CMT2380F17 21.3 Using the TWI/ I2C The TWI/ I2C is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI/ I2C is interrupt-based, the application software is free to carry on other operations during a TWI/ I2C byte transfer. Note that the TWI/ I2C0 interrupt enable bit ETWI/ I2C0 bit (EIE1.6) together with the EA bit allow the application to decide...
  • Page 263 CMT2380F17 (1) Master/Transmitter Mode Set STA to generate a START From Slave Mode A START has been transmitted (STA,STO,SI,AA)=(0,0,0,X) SLA+W will be transmitted; ACK bit will be received. From Master/Receiver SLA+W will be transmitted; ACK bit will be received. SLA+W will be transmitted;...
  • Page 264 CMT2380F17 (2) Master/Receiv er Mode Set STA to generate a START. From Slave Mode A START has been transmitted. (STA,STO,SI,AA)=(0,0,0,X) SLA+R will be transmitted; ACK will be received. From Master/Transmitter SLA+R has been transmitted; SLA+R has been transmitted; NOT ACK has been received.
  • Page 265 CMT2380F17 (3) Slav e/Transmitter Mode Set AA Own SLA+R has been received; ACK has been returned. Arbitration lost in SLA+R/W as master; Own SLA+R has been received; ACK has been returned. (STA,STO,SI,AA)=(0,0,0,0) (STA,STO,SI,AA)=(0,0,0,1) Last data byte will be transmitted; Data byte will be transmitted;...
  • Page 266 CMT2380F17 (4) Slav e/Receiv er Mode Set AA Own SLA+W has been received; ACK has been returned. Arbitration lost in SLA+R/W as master; Own SLA+W has been received; ACK has been returned. (STA,STO,SI,AA)=(0,0,0,0) (STA,STO,SI,AA)=(0,0,0,1) Data byte will be received; Data byte will be received;...
  • Page 267 CMT2380F17 (5) Slav e/Receiv er Mode (For General Call) Set AA General Call address has been received; ACK has been returned. Arbitration lost in SLA+R/W as master; General Call address has been received; ACK has been returned. (STA,STO,SI,AA)=(0,0,0,0) (STA,STO,SI,AA)=(0,0,0,1) Data byte will be received;...
  • Page 268: Twi0/ I2C0 Register

    CMT2380F17 21.4 TWI0/ I2C0 Register  SIADR:TWI0/ I2C0 Address Register SFR Page = 0~F SFR Address = 0xD1 Name Reset V alue The CPU can read from and write to this register directly. SIADR is not affected by the TWI0/ I2C0 hardware.
  • Page 269 CMT2380F17  SICON:TWI0/ I2C0 Control Register SFR Page = 0~F SFR Address = 0xD4 Name ENSI Reset V alue The CPU can read and write to this register directly. Two bits are affected by the TWI0/I2C0 hardware: the SI will be set when a serial interrupt occurred, and the STO will be cleared when a STOP condition is present on the bus.
  • Page 270 CMT2380F17 If the AA flag is reset to “0”, a not acknowledge (high level to TWI0_SDA) will be returned during the acknowledge clock pulse on TWI0_SCL when: A data has been received while TWI0/I2C0 is in the master/receiver mode. A data byte has been received while TWI0/I2C0 is in the addressed slave/receiver mode.
  • Page 271 CMT2380F17 Reset V alue Bit 2~1: TWIPS1~0, TWI0/ I2C0 Port Selection [1:0]. TWIPS[1:0] TWI0/I2C0_SCL TWI0/I2C0_SDA P3.1 P3.0 P6.0 P6.1 P3.0 P3.1 P2.2 P2.4  AUXR10:Auxiliary Register 10 SFR Page = 7 only SFR Address = 0xA4 SPIPS0 S0PS1 TWICF Name Reset V alue Bit 1: TWICF, TWI0/I2C0 serial Clock input Filter.
  • Page 272: Serial Interface Detection (Stwi/Si2C)

    CMT2380F17 22 Serial Interface Detection (STWI/SI2C) The serial interface detection module (SID) is always monitoring the “Start” and “Stop” condition on software two-wire-interface (STWI/SI2C). STWI_SCL is the serial clock signal and STWI_SDA is the serial data signal. If any matched condition is detected, hardware set the flag on STAF and STOF. Software can poll these two flags or set SIDFIE (SFIE.7) to share the interrupt vector on System Flag.
  • Page 273 CMT2380F17 SFR Address = 0x8E RESET = 0110-x000 SIDFIE RTCFIE BOF1IE BOF0IE WDTFIE Name Reset V alue Bit 7: SIDFIE, Serial Interface (STWI/SI2C) Detection Flag Interrupt Enabled. 0: Disable SID Flags (STAF or STOF) interrupt. 1: Enable SID Flags (STAF or STOF) interrupt.
  • Page 274: Beeper

    CMT2380F17 23 Beeper The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range about 1, 2 or 4 kHz which is divided from ILRCO. Figure 23–1 shows the beeper generator circuit. But ILRCO is not the precision clock source.
  • Page 275 CMT2380F17  DCON0:Device Control 0 SFR Page = P Only SFR Address = 0x4C IAPO HSE1 IORCTL RSTIO OCDE Name Reset V alue Bit 0: OCDE, OCD enable. 0: Disable OCD interface on P4.4 and P4.5 1: Enable OCD interface on P4.4 and P4.5.
  • Page 276: Keypad Interrupt (Kbi)

    CMT2380F17 24 Keypad Interrupt (KBI) The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when KBI.7~0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition.
  • Page 277 CMT2380F17 KBPATN[7:0] Name Reset V alue Bit 7~0: KBPATN.7~0: The keypad pattern, reset value is 0xFF.  KBCON:Keypad Control Register SFR Page = 0~F SFR Address = 0xD6 KBCS[1:0] KBES PATN_SEL KBIF Name Reset V alue Bit 7~6: KBCS1~0, KBI Filter mode control.
  • Page 278 CMT2380F17 KBI4PS1 KB4IPS0 KBI6PS0 KBI2PS0 T3FCS T2FCS SnMIPS S0COPS Name Reset V alue Bit 7~6: KBI4PS1~0, KBI4~5 Port pin Selection [1:0]. KBI4PS1~0 KBI4 KBI5 P3.3 P1.5 P3.4 P3.5 P6.0 P6.1 P1.5 P3.3 Bit 5: KBI6PS0, KBI6~7 Port pin Selection 0.
  • Page 279: General Purpose Logic (Gpl-Crc)

    CMT2380F17 25 General Purpose Logic (GPL-CRC) The CMT2380F17 builds in a general purpose logic cyclic redundancy check function with CCITT16 (CRC16 0x1021) polynomial. The CRC accepts a stream of 8-bit data written to the CRC0DI. Its initial value (seed value) is programmable for multi-purpose applications. The 16-bit initial value (seed value) is set to high byte CRC0SH (CRCDS0~1=01) and low byte CRC0SL (CRCDS0~1=00).
  • Page 280: Gpl-Borev Structure

    CMT2380F17 25.2 GPL-BOREV Structure Figure 25–2. GPL-BOREV Structure 25.3 GPL Register The following special function registers are related to the CRC operation:  CRC0DA: CRC0 Data Port SFR Page = 0~F SFR Address = 0xB6 CRC0DA[7:0] Name Reset V alue Bit 7~0: CRC0 Data Port.
  • Page 281 CMT2380F17 SFR Page = 0~F SFR Address = 0x96 BOREV[7:0] Name Reset V alue Bit 7~0: BOREV7~0, data read/write for Bit-Order-Reversed function. Any byte written to BOREV is read back in a bit-reversed order, i.e., the written LSB becomes the MSB.
  • Page 282: 12-Bit Adc

    CMT2380F17 26 12-Bit ADC The ADC subsystem for the CMT2380F17 consists of an analog multiplexer (AMUX), and a 800K sps, 12-bit successive-approximation-register ADC. The AMUX can be configured via the Special Function Registers shown in Figure 26–1. ADC operates in Single-ended mode, and may be configured to measure any of the pins on Port 1 or internal reference.
  • Page 283: Adc Operation

    CMT2380F17 26.2 ADC Operation ADC has a maximum conversion speed of 800 ksps. The ADC conversion clock is a divided version of the system clock, S0 BRG overflow or Timer 2 overflow, determined by the ADCKS2~0 bits in the ADCFG0 register.
  • Page 284: Adc Conversion Rate

    (In this case, the AC input signal fN frequency should lower than 75KHz to ensure the measurement accuracy.) 26.2.5 ADC Interrupts The ADC interrupt of CMT2380F17 includes 3 sources: ADCI, when an A/D conversion is completed, ADCI will be set to invoke an interrupt. The interrupt on this flag can be blocked by IGADCI (ADCFG1.7).
  • Page 285: Adc Window Detect

    CMT2380F17 Figure 26–3. ADC Conversion Timing 26.2.6 ADC Window Detect The MG82F6D17 ADC's programmable window detector continuously compares the ADC output registers with user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt driven system, saving code space and CPU bandwidth while delivering faster response times.
  • Page 286: Adc Channel Scan Mode

    26.2.7 ADC Channel Scan Mode CMT2380F17 has 8 channels used as ADC input. If the application needs to watch serval voltage by different input pad sequentially, to use ADC Channel Scan Mode can be the easy way to implement and save the channel switch time.
  • Page 287: I/O Pins Used With Adc Function

    CMT2380F17 Data Transfer Order ARES[1:0] DBSD ADRJ Data Data ADC Data Resolution ADC Data Byte Transfer by DMA 0xF0 0xFF (2-byte Data) 0xFF (12-bit) (1-byte Data) 0xC0 0xFF (2-byte Data) 0xFF (10-bit) (1-byte Data) 0x00 0xFF (2-byte Data) 0xFF (8-bit)
  • Page 288: Adc Register

    CMT2380F17 Note: To read the IVR ADC Presorted value please reference 27.3 How to read IVR (1.4V) ADC Prestored value . 26.3 ADC Register  ADCON0:ADC Control Register 0 SFR Page = 0~F SFR Address = 0xC4 Name ADCEN ADCWI...
  • Page 289 CMT2380F17 www.cmostek.com Rev0.1 | 289/347...
  • Page 290 CMT2380F17  ADCFG0:ADC Configuration Register 0 SFR Page = 0 Only SFR Address = 0xC3 ADCKS[2:0] ADRJ ACHS SMPF ADTM1 ADTM0 Name Reset V alue Bit 7~5: ADC Conversion Clock Select bits. ADCKS[2:0] ADC Clock Selection 0 0 0 SYSCLK...
  • Page 291 CMT2380F17  ADCL: ADC Data Low Byte Register SFR Page = 0~F SFR Address = 0xC5 ADCD[3:0] Name Reset V alue (2) If ADRJ = 1  ADCDH ADCD[11:8] Name Reset V alue  ADCDL ADCD[7:0] Name Reset V alue When in Single-ended Mode, conversion codes are represented as 12-bit unsigned integers.
  • Page 292 CMT2380F17 Reset V alue Bit 7: IGADCI, Ignore ADCI interrupt. 0: Enabled ADCI interrupt. Default is enabled. 1: Disable ADCI interrupt. Bit 6: EADCWI, ADCWI interrupt enable. 0: Disable ADCWI interrupt. 1: Enable ADCWI interrupt to share the ADC interrupt vector.
  • Page 293 CMT2380F17 Medium low power, medium low speed Low power, low speed Bit 5~4: Reserved. Software must write “0” on these bits when ADCFG3 is written. Bit 3~2: ARES1~0, ADC data Resolution selection bit 1~0. ARES[1:0] ADC Data Resolution Selection 12-bit Data...
  • Page 294 CMT2380F17 2 Bytes Data 1 Byte Data Bit 0: Reserved. Software must write “0” on this bit when ADCFG4 is written.  ADCFG5:ADC Configuration Register 5 SFR Page = 5 only SFR Address = 0xC3 ASCE[7:0] Name Reset V alue Bit 7~0: AIN7~AIN0 auto-scan enabled.
  • Page 295 CMT2380F17  PCON3:Power Control Register 3 SFR Page = P Only SFR Address = 0x45 Name IVREN Reset V alue Bit 7: IVREN, Internal Voltage Reference Enable. 0: Disable on-chip IVR (1.4V). 1: Enable on-chip IVR (1.4V). Bit 6~0: Reserved. Software must write “0” on these bits when PCON3 is written.
  • Page 296: Internal Voltage Reference (Ivr, 1.4V)

    CMT2380F17 27 Internal Voltage Reference (IVR, 1.4V) The IVR can be used as the reference voltage of the ADC. The typical output is 1.4V. It can be disabling by IVREN. 27.1 IVR (1.4V) Structure Figure 25-1. IVR Diagram 27.2 IVR Register ...
  • Page 297 CMT2380F17 SCMD = 0x46; SCMD = 0xB9; Trim_IVR_ADC_Value.B[0] = IFD; IFADRL ++; SCMD = 0x46; SCMD = 0xB9; Trim_IVR_ADC_Value.B[1] = IFD; ISPCR = ISP_DISABLE; www.cmostek.com Rev0.1 | 297/347...
  • Page 298: Isp And Iap

    MCU is running in AP region, software could only modify the IAP memory for storage data updated.。 28.1 CMT2380F17 Flash Memory Configuration There are total 16K bytes of Flash Memory in CMT2380F17 and Figure 28–1 shows the device flash configuration of MG82F6D17. The ISP-memory can be configured as disabled or up to 7.5K bytes space by hardware option setting with 0.5KB step.
  • Page 299: Isp/Iap Flash Page Erase Mode

    28.2.1 ISP/IAP Flash Page Erase Mode The any bit in flash data of CMT2380F17 only can be programmed to “0”. If user would like to write a “1” into flash data, the flash erase is necessary. But the flash erase in MG82F6D17 ISP/IAP operation only support “page erase”...
  • Page 300 CMT2380F17 Start Define ISP/IAP ==> Configure CKCON1.XCKS5~0 time base Enable ISP/IAP ==> Set ISPCR.ISPEN = "1" engine Set "Page Erase" ==> Write IFMT.MS2~0 = "011" Mode Define targeted ==> Define IFADRH & IFADRL flash page address Trigger engine for ==> Write SCMD = 0x46, then ==>...
  • Page 301: Isp/Iap Flash Byte Program Mode

    28.2.2 ISP/IAP Flash Byte Program Mode The “program” mode of CMT2380F17 provides the byte write operation into flash memory for new data updated. The IFADRH and IFADRL point to the physical flash byte address. IFD stores the content which will be programmed into the flash.
  • Page 302 CMT2380F17 Figure 28-5. Demo Code for ISP/IAP Byte Program ISPCR, #10000011b ; ISPCR.7=1, enable ISP IFMT, #02h ; select Program Mode IFADRH, ?? ; fill [IFADRH,IFADRL] with byte addres IFADRL, ?? IFD, ?? ; fill IFD with the data to be programmed SCMD, #46h ;...
  • Page 303: Isp/Iap Flash Read Mode

    28.2.3 ISP/IAP Flash Read Mode The “read” mode of CMT2380F17 provides the byte read operation from flash memory to get the stored data. The IFADRH and IFADRL point to the physical flash byte address. IFD stores the data which is read from the flash content.
  • Page 304: Isp Operation

    CMT2380F17 Figure 28-7. Demo Code for ISP/IAP byte Read ISPCR, #10000011b ; ISPCR.7=1, enable ISP IFMT, #01h ; select Read Mode IFADRH, ?? ; fill [IFADRH,IFADRL] with byte address IFADRL, ?? SCMD, #46h ; fill [IFADRH,IFADRL] with byte address SCMD, #0B9h ;...
  • Page 305: Software Approached Isp

    CMT2380F17 28.3.2 Software approached ISP The software approached ISP to make the MCU boot from the ISP-memory is to trigger a software reset while the MCU is running in the AP-memory. In this case, neither HWBS nor HWBS2 is enabled. The only way for the MCU to boot from the ISP-memory is to trigger a software reset, setting ISPCR.7~5 to “111”...
  • Page 306: In-Application-Programming (Iap)

    CMT2380F17 28.4 In-Application-Programming (IAP) The CMT2380F17 has built a function as In Application Programmable (IAP), which allows some region in the Flash memory to be used as non-volatile data storage while the application program is running. This useful feature can be applied to the application where the data must be kept after power off. Thus, there is no need to use an external serial EEPROM (such as 93C46, 24C01, .., and so on) for saving the non-volatile...
  • Page 307: Notes For Iap

    CMT2380F17 28.4.3 Notes for IAP Interrupts during IAP After triggering the ISP/IAP flash processing for In-Application Programming, the MCU will halt for a while for internal IAP processing until the processing is completed. At this time, the interrupt will queue up for being serviced if the interrupt is enabled previously.
  • Page 308 CMT2380F17 IFD is the data port register for ISP/IAP/Page-P operation. The data in IFD will be written into the desired address in operating ISP/IAP/Page-P write and it is the data window of readout in operating ISP/IAP read.  IFADRH:ISP/IAP Address for High-byte addressing...
  • Page 309 CMT2380F17  IFMT:ISP/IAP Flash Mode Table SFR Page = 0~F SFR Address = 0xE5 MS[7:0] Name Reset V alue Bit 7~4: Reserved. Software must write “0000_0” on these bits when IFMT is written. Bit 3~0: ISP/IAP/Page-P operating mode selection. MS[7:0]...
  • Page 310: Isp/Iap Sample Code

    CMT2380F17 Bit 5: SWRST, software reset trigger control. 0: No operation 1: Generate software system reset. It will be cleared by hardware automatically. Bit 4: CFAIL, Command Fail indication for ISP/IAP operation. 0: The last ISP/IAP command has finished successfully.
  • Page 311 CMT2380F17 IFMT,#02h ;MS[2:0]=[0,1,0], slect Byte Program Mode ISPCR,#0FAh ; IFADRH,?? ;fill byte address in IFADRH & IFADRL IFADRL,?? IFD,?? ;fill the data to be programmed in IFD SCMD,#46h ;trigger ISP processing SCMD,#0B9h ; ;Now in processing...(CPU will halt here until complete) ;=============================================================================...
  • Page 312: Page P Sfr Access

    CMT2380F17 29 Page P SFR Access CMT2380F17 builds a special SFR page (Page P) to store the control registers for MCU operation. These SFRs can be accessed by the ISP/IAP operation with different IFMT. In page P access, IFADRH must set to “00”...
  • Page 313 CMT2380F17 OSCin 12MHz 11.059MHz CKMI x4/x6 24MHz 36MHz 22.118MHz 33.177MHz CKMI x5.33/x8 32MHz 48MHz 29.491MHz 44.236MHz CKMI x8/x12 48MHz 72MHz 44.236MHz 66.354MHz Note: It needs to set ENCKM = 1 to enable CKM. Note: Needs to be careful of the limitation of CPUCLK and SYSCLK. Needs to use SCKS[2:0] and CCKS ≤...
  • Page 314 CMT2380F17 RCSS2 RCSS1 RCSS0 RPSC2 RPSC1 RPSC0 RTCCS3 RTCCS2 Name Reset V alue Bit 7~5: RTC Clock Source selection [2:0] RCSS[2:0] RTC Clock Selection 0 0 0 ECKI(P6.0) 0 0 1 ILRCO 0 1 0 WDTPS 0 1 1 WDTOF...
  • Page 315 CMT2380F17 Disable BOD1 to slow down the chip power consumption. 1: Enable BOD1 to monitor VDD power dropped. Bit 1: BO0RE, BOD0 Reset Enabled. 0: Disable BOD0 to trigger a system reset when BOF0 is set. 1: Enable BOD0 to trigger a system reset when BOF0 is set (VDD meets 1.7V).
  • Page 316 CMT2380F17 SFR Page = P Only SFR Address = 0x4C C IAPO HSE1 IORCTL RSTIO OCDE Name Reset V alue Bit 7: HSE, High Speed operation Enable. 0: Select CPU running in lower speed mode (FCPUCLK ≤ 6MHz) which is slow down internal circuit to reduce power consumption.
  • Page 317: Auxiliary Sfrs

    CMT2380F17 30 Auxiliary SFRs 30.1 SFR Figure(Page 0~F) CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H CCAP5H CCAP6H CCAP7H PCAPWM0 PCAPWM1 PAOE PCAPWM2 PCAPWM3 PCAPWM4 PCAPWM5 PCAPWM6 PCAPWM7 CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L CCAP5L CCAP6L CCAP7L WDTCR IFADRH IFADRL IFMT SCMD ISPCR CCAPM0...
  • Page 318: Sfr Bit Assignment (Page 0~F)

    CMT2380F17  SFRPI: SFR Page Index Register SFR Page = 0~F SFR Address = 0xAC Name PIDX3 PIDX2 PIDX1 PIDX0 Reset V alue Bit 7~4: Reserved. Software must write “0” on these bits when SFRPI is written. Bit 3~0: SFR Page Index.
  • Page 319 CMT2380F17 BIT ADDRESS AND SYMBOL RESET ADDR PAGE SYMBOL DESCRIPTION (HEX) (HEX) VALUE Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Timer Run Enable TREN0 TR3LE TR2LE TR3E TR2E TR1E TR0E x00x0000 Register 0 Timer Reload Control TRLC0 TL3RLC TL2RLC...
  • Page 320 CMT2380F17 BIT ADDRESS AND SYMBOL RESET ADDR PAGE SYMBOL DESCRIPTION (HEX) (HEX) VALUE Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 ADCFG5 ADC Configuration 5 ASCE.7 ASCE.6 ASCE.5 ASCE.4 ASCE.3 ASCE.2 ASCE.1 ASCE.0 00000000 ADCFG11 ADC Configuration 11 WHB.3 WHB.2 WHB.1...
  • Page 321 CMT2380F17 BIT ADDRESS AND SYMBOL RESET ADDR PAGE SYMBOL DESCRIPTION (HEX) (HEX) VALUE Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 CCAP3L module3 00000000 capture Low CCAP4L module4 00000000 capture Low CCAP5L module5 00000000 capture Low B Register 00000000 PWM Additional Output...
  • Page 322: Auxiliary Sfr Map

    30.3 Auxiliary SFR Map (Page P) CMT2380F17 has an auxiliary SFR page which is indexed by page P and the SFRs’ write is a different way from standard 8051 SFR page. The registers in auxiliary SFR map are addressed by IFMT and SCMD like ISP/IAP access flow.
  • Page 323 CMT2380F17 CKCON4 Clock Control 4 RCSS2 RCSS1 RCSS0 RPSC2 RPSC1 RPSC0 RTCCS3 RTCCS2 00000000 CKCON5 Clock Control 5 CKMS0 00000000 PCON2 Power Control 2 44H AWBOD1 BO1S1 BO1S0 BO1RE EBOD1 BO0RE 0000x1x1 PCON3 Power Control 3 IVREN 00000000 Page SPCON0...
  • Page 324: Auxiliary Sfr Register

    CMT2380F17 30.5 Auxiliary SFR Register  AUXR0:Auxiliary Register 0 SFR Page = 0~F SFR Address = 0xA1 Name P60OC1 P60OC0 P60FD PBKF INT1H INT0H Reset V alue Bit 7~6: P6.0 function configured control bit 1 and 0. The two bits only act when internal RC oscillator (IHRCO or ILRCO) is selected for system clock source.
  • Page 325 CMT2380F17 Bit 3~1: Reserved bits. When AUXR1 is written, the software must write "0" to these bits. Bit 0: DPS, DPTR select bit. Use to switch between DPTR0 and DPTR1. 0: Select DPTR0. 1: Select DPTR1. DPTR Selection DPTR0 DPTR1 ...
  • Page 326 CMT2380F17 P3.4 P4.4 P2.2 P1.7 Bit 5~4: T1PS1~0, Timer 1 Port pin Selection [1:0]. P4.4 Function I/O Mode BPOC[1:0] P4.4 By P4M0.4 & P4M1.4 ILRCO/32 By P4M0.4 & P4M1.4 ILRCO/16 By P4M0.4 & P4M1.4 ILRCO/8 By P4M0.4 & P4M1.4 The buzzer function is in P4.4, it is recommended to set P4.4 to work in push-pull output mode.
  • Page 327 CMT2380F17 Bit 3: S0PS0, serial port 0 (UART0) port pin selection bit 0. (S0PS1 is in AUXR10.3) S0PS1, S0PS0 RXD0 TXD0 P3.0 P3.1 P4.4 P4.5 P3.1 P3.0 P1.7 P2.2 Bit 2~1: TWIPS1~0, TWI0 port pin selection bits[1:0]. TWIPS1~0 TWI0_SCL TWI0_SDA P3.1...
  • Page 328 CMT2380F17  AUXR5: Auxiliary Register 5 SFR Page = 2 only SFR Address = 0xA4 Name C0IC4S0 C0IC2S0 C0PPS1 C0PPS0 C0PS0 ECIPS0 C0COPS Reset V alue Bit 7: C0IC4S0, PCA0 Input Channel 4 input port pin Selection. C0IC4S0 CEX4 input...
  • Page 329 CMT2380F17 P3.3 P1.5 P3.4 P3.5 P6.0 P6.1 P1.5 P3.3 Bit 5: KBI6PS0, KBI6~7 Port pin Selection 0. KBI6PS0 KBI6 KBI7 P1.6 P1.7 P3.0 P3.1 Bit 4: KBI2PS0, KBI2~3 Port pin Selection 0. KBI2PS0 KBI2 KBI3 P3.0 P3.1 P2.2 P2.4 Bit 3: T3FCS, Reserved for chip test.
  • Page 330 CMT2380F17  AUXR8: Auxiliary Register 8 SFR Page = 5 only SFR Address = 0xA4 Name POE7 POE6 C0PPS2 KBI0PS0 S1COPS Reset V alue Bit 7: POE7, PCA0 PWM7 main channel (PWM7O) output control. 0: Disable PWM7O output on port pin.
  • Page 331 CMT2380F17 Bit 1~0: S1PS1~0, Serial Port 1 pin Selection [1:0]. T1 Gate Control T1G1, T1GATE Source Disabled INT1 activation TF3 activation TI1 activation Bit 4:T0G1, Timer 0 gate control source selection. T0 Gate Control T0G1, T0GATE Source Disabled INT0 activation...
  • Page 332 CMT2380F17 Reset V alue Bit 1: C0M0, PCA0 Mode control 0. 0: Not support variable resolution on central aligned PWM. 1: Enable PCA0 variable resolution central aligned PWM. To enable this function, the PCAE also needs to be set. Bit 0: C0OFS, PCA0 overflow flag selection when C0M0 is enabled.
  • Page 333: Hardware Option

    Writer U1” or the “Megawin 8051 ICE Adapter” (The ICE adapter also supports ICP programming function. Refer Section “32.4 In-Chip-Programming Function”). After whole-chip erased, all the hardware options are left in “disabled” state and there is no ISP-memory and IAP-memory configured. The CMT2380F17 has the following Hardware Options: LOCK: ...
  • Page 334 CMT2380F17 BO1S1O, BO1S0O:  ,: Select BOD1 to detect 2.0V.  ,: Select BOD1 to detect 2.4V. ,: Select BOD1 to detect 3.7V. ,: Select BOD1 to detect 4.2V. BO0REO:  : Enabled. BOD0 will trigger a RESET event to CPU on AP program start address. (1.7V) : Disabled.
  • Page 335: Application Notes

    CMT2380F17 32 Application Notes 32.1 Power Supply Circuit To have the CMT2380F17 work with power supply varying from 2.0V to 5.5V, adding some external decoupling and bypass capacitors is necessary, as shown in Figure 32–1. Power Supply 0.1uF 10uF 0.1uF 4.7uF...
  • Page 336: In-Chip-Programming Function

    OCED as “1”. Or “Erase” the on-chip flash by ICP which cleans the user software to stop the port pins switching. However, for the CMT2380F17 SOP8 package it does not support ICP due to the pin limitation. For SOP8 package, it is necessary to use other package within code development phase. Once the code has been done and then use the ISP to download the code for physical evaluation.。...
  • Page 337: On-Chip-Debug Function

    "Megawin 8051 OCD ICE" Figure 32-4. Stand-alone programming via ICP 32.5 On-Chip-Debug Function The CMT2380F17 is equipped with a Megawin proprietary On-Chip Debug (OCD) interface for In-Circuit Emulator (ICE). The OCD interface provides on-chip and in-system non-intrusive debugging without any target resource occupied.
  • Page 338 CMT2380F17  Features OCD (On-Chip-Debug) technology On-chip & in-system real-time debugging 5-pin dedicated serial interface for OCD, no target resource occupied Directly linked to the debugger function of the Keil 8051 IDE Software USB connection between target and host (PC)
  • Page 339: Instruction Set

    CMT2380F17 33 Instruction Set EXECUTION MNEMONIC DESCRIPTION BYTE Cycles DATA TRASFER MOV A,Rn Move register to Acc MOV A,direct Move direct byte o Acc MOV A,@Ri Move indirect RAM to Acc MOV A,#data Move immediate data to Acc MOV Rn,A...
  • Page 340 CMT2380F17 ADDC A,#data Add immediate data to Acc with Carry SUBB A,Rn Subtract register from Acc with borrow SUBB A,direct Subtract direct byte from Acc with borrow SUBB A,@Ri Subtract indirect RAM from Acc with borrow SUBB A,#data Subtract immediate data from Acc with borrow...
  • Page 341 CMT2380F17 CPL C Complement Carry CPL bit Complement direct bit ANL C,bit AND direct bit to Carry ANL C,/bit AND complement of direct bit to Carry ORL C,bit OR direct bit to Carry ORL C,/bit OR complement of direct bit to Carry...
  • Page 342: Ordering Information

    R refers to tape and tray type, and the minimum order quantity (MOQ) is 3,000 pieces. Please visit www.cmostek.com for more product/product line information. Please contact sales@cmostek.comor your local sales representative for sales or pricing requirements. www.cmostek.com Rev0.1 | 342/347...
  • Page 343: Packaging Information

    CMT2380F17 35 Packaging Information The packaging information of the CMT2380F17 is shown in the below figure. EXPOSED THERMAL Top View Bottom View PAD ZONE Side View Figure 35-1. QFN40 5x5 Packaging Table 35-1. QFN40 5x5 Packaging Scale Scale (mm) Symbol Maximum Min.
  • Page 344: Top Marking

    36 Top Marking 2 3 8 0 F 1 7 E 9 ① ② Figure 36-1. The CMT2380F17 Top Marking Table 36-2. The CMT2380F17 Top Marking Information Marking Method Laser Pin 1 Mark Diameter of the circle = 0.3 mm Font Size 0.5 mm, align right...
  • Page 345: Reference Documents

    AN142 CMT2300A Quick Start Guide CMT2380F17 RF quick start guidelines. AN143 CMT2300A FIFO and Packet Format Usage Guide CMT2380F17 RF transceiver message usage guide. AN144 CMT2300A RSSI User Guide CMT2380F17 RF RSSI user guide. AN146 CMT2300A Low Power Mode User Guide CMT2380F17 RF Low power design guidelines.
  • Page 346: Revise History

    CMT2380F17 38 Revise History Table 38-1. Revise History Records Version No. Chapter Description Date Inital version 2021-10-19 www.cmostek.com Rev0.1 | 346/347...
  • Page 347: Contacts

    The material contained herein is the exclusive property of CMOSTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of CMOSTEK. CMOSTEK products are not authorized for use as critical components in life support devices or systems without express written approval of CMOSTEK.

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