CMOSTEK CMT2380F17 Manual page 269

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SICON：TWI0/ I2C0 Control Register
SFR Page = 0~F
SFR Address = 0xD4
Bit
7
Name CR2
R/W R/W
Reset V alue 0
The CPU can read and write to this register directly. Two bits are affected by the TWI0/I2C0 hardware:
the SI will be set when a serial interrupt occurred, and the STO will be cleared when a STOP condition is
present on the bus. The STO bit is also cleared when ENSI="0".
Bit 7: CR2, TWI0/ I2C0 Clock Rate select bit 2 (associated with CR1 and CR0). Bit 6: ENSI, the
TWI0/I2C0 Hardware Enable Bit
When ENSI is "0", the TWI0 _SDA and TWI0_SCL outputs are in a high impedance state, and it will
ignore the input signals. Under this condition, the TWI0/I2C0 is in the not-addressed slave state, and STO is
forced to "0". No other bits are affected, and the TWI0_SDA and TWI0_SCL can be used as general purpose
I/O pins. When ENSI is "1", TWI0 is enabled, the TWI0_SDA and TWI0_SCL assign to port pin latch, such as
P4.1 and P4.0. The port pin latch must be set to logic 1 and I/O mode must be configured to open-drain mode
for the serial communication.
Bit 5: STA, the START Flag
When sets the STA to enter master mode, the TWI0/I2C0 hardware will check the status of the serial bus.
It will generate a START condition if the bus is free. Otherwise TWI0/I2C0 will wait for a STOP condition and
generates a START condition after a delay. If STA is set while TWI0/I2C0 is already in a master mode and one
or more bytes are transmitting or receiving, TWI0/I2C0 will send a repeated START condition. STA may be set
at any time. STA may also be set when TWI0/I2C0 is an addressed slave mode. When the STA bit is reset, no
START condition or repeated START condition will be generated.
Bit 4: STO, the STOP Flag
When the STO is set while TWI0/I2C0 is in a master mode, a STOP condition is transmitted to the serial
bus. When the STOP condition is detected on the bus, the TWI0/I2C0 hardware clears the STO flag. In a
slave mode, the STO flag may be set to recover from a bus error condition. In this case, no STOP condition is
transmitted to the bus. However, the TWI0/I2C0 hardware behaves as if a STOP condition has been received
and switches to the defined not addressed slave receiver mode. The STO flag is automatically cleared by
hardware. If the STA and STO bits are both set, then a STOP condition is transmitted to the bus if TWI0/I2C0
is in a master mode (in a slave mode, TWI0/I2C0 generates an internal STOP condition which is not
transmitted), and then transmits a START condition.
Bit 3: SI, the Serial Interrupt Flag
When a new TWI0/I2C0 state is present in the SISTA register, the SI flag is set by hardware. And, if the
TWI0/I2C0 interrupt is enabled, an interrupt service routine will be serviced. The only state that does not
cause SI to be set is state F8H, which indicates that no relevant state information is available. When SI is set,
the low period of the serial clock on the TWI0_SCL line is stretched, and the serial transfer is suspended. A
high level on the TWI0_SCL line is unaffected by the serial interrupt flag. SI must be cleared by software
writing "0" on this bit. When the SI flag is reset, no serial interrupt is requested, and there is no stretching on
the serial clock on the TWI0_SCL line.
Bit 2: AA, the Assert Acknowledge Flag
If the AA flag is set to "1", an Acknowledge (low level to TWI0_SDA) will be returned during the
acknowledge clock pulse on the TWI0_SCL line when:
1) The own slave address has been received.
2) A data byte has been received while TWI0/I2C0 is in the master/receiver mode.
3) A data byte has been received while TWI0/I2C0 is in the addressed slave/receiver mode.
6 5
ENSI STA
R/W R/W
0 0
Rev0.1 | 269/347
4 3
STO SI
R/W R/W
0 0
CMT2380F17
2 1
AA CR1
R/W R/W
0 0
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0
CR0
R/W
0