Global Control For All Timer Stop - CMOSTEK CMT2380F17 Manual

16.4.3 Global Control for all Timer Stop


TSPC0：Timer Stop Control Register 0
SFR Page = 3 Only
SFR Address = 0x95
Bit
7
Name --
R/W R/W
Reset V alue
0
Bit 7: Reserved. Software must write "0" on this bit when TSPC0 is written.
Bit 6, TL3SC, write "1" on this bit to set TR3L disabled (TR3L=0) when Timer 3 in split mode. This bit is
auto-cleared by hardware after writing "1" operation. Write "0" on this bit is no action.
Bit 5, TL2SC, write "1" on this bit to set TR2L disabled (TR2L=0) when Timer 2 in split mode. This bit is
auto-cleared by hardware after writing "1" operation. Write "0" on this bit is no action.
Bit 4: Reserved. Software must write "0" on this bit when TSPC0 is written.
Bit 3, T3SC, write "1" on this bit to set TR3 disabled (TR3=0). This bit is auto-cleared by hardware after
writing "1" operation. Write "0" on this bit is no action.
Bit 2, T2SC, write "1" on this bit to set TR2 disabled (TR2=0). This bit is auto-cleared by hardware after
writing "1" operation. Write "0" on this bit is no action.
Bit 1, T1SC, write "1" on this bit to set TR1 disabled (TR1=0). This bit is auto-cleared by hardware after
writing "1" operation. Write "0" on this bit is no action.
Bit 0, T0SC, write "1" on this bit to set TR0 disabled (TR0=0). This bit is auto-cleared by hardware after
writing "1" operation. Write "0" on this bit is no action.
RESET= 0000-0000
6 5
TL3SC TL2SC
R/W R/W
0 0
Rev0.1 | 172/347
4 3
-- T3SC
R/W R/W
0 0
CMT2380F17
2 1
T2SC T1SC
W R/W
X 0
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0
T0SC
R/W
0