Alinx AC7Z100 User Manual page 9

sides respectively. Two DDR3 SDRAMs form a 32-bit bus width. The PS-side
DDR3 SDRAM has a maximum operating speed of 533MHz (data rate
1066Mbps), and two DDR3 memory systems are directly connected to the
memory interface of the BANK 502 of the ZYNQ Processing System (PS). The
PL-side DDR3 SDRAM has a maximum operating speed of 800MHz (data rate
1600Mbps), and two DDR3 memory systems are connected to the BANK33
and BANK34 interfaces of the FPGA. The specific configuration of DDR3
SDRAM is shown in Table 3-1.
Bit Number
U4,U5,U7,U8
The hardware design of DDR3 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR3.
Figure 3-1: The Schematic Part of DDR3 DRAM on the PS side
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ZYNQ FPGA Development Board AC7Z100 User Manual
Chip Model
MT41J256M16HA-125
Table 3-1: DDR3 SDRAM Configuration
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Capacity Factory
256M x 16bit Micron