Alinx AC7Z100 User Manual page 19

PL system clock source
The differential 200MHz PL system clock source is provided on the FPGA
core board AC7Z100 for the reference clock of the DDR3 controller. The crystal
output is connected to the global clock (MRCC) of the FPGA BANK34, which
can be used to drive the DDR3 controller and user logic in the FPGA. The
schematic diagram of the clock source is shown in Figure 6-3
PL Clock pin assignment:
GTX reference clock
The FPGA core board AC7Z100 provides a 125Mhz reference clock for
the GTX transceiver. The reference clock is connected to the reference clock
input REFCLK1P/REFCLK1N of the BANK111. The schematic diagram of the
clock source is shown in Figure 6-4.
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ZYNQ FPGA Development Board AC7Z100 User Manual
Figure 6-3: PL system clock source
Signal Name
SYS_CLK_P
SYS_CLK_N
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ZYNQ Pin
F9
E8