Alinx AC7Z100 User Manual page 12

PS_DDR3_A6
PS_DDR3_A7
PS_DDR3_A8
PS_DDR3_A9
PS_DDR3_A10
PS_DDR3_A11
PS_DDR3_A12
PS_DDR3_A13
PS_DDR3_A14
PS_DDR3_BA0
PS_DDR3_BA1
PS_DDR3_BA2
PS_DDR3_S0
PS_DDR3_RAS
PS_DDR3_CAS
PS_DDR3_WE
PS_DDR3_ODT
PS_DDR3_RESET
PS_DDR3_CLK0_P
PS_DDR3_CLK0_N
PS_DDR3_CKE
PL side DDR3 DRAM pin assignment:
Signal Name
PL_DDR3_DQS0_P
PL_DDR3_DQS0_N
PL_DDR3_DQS1_P
PL_DDR3_DQS1_N
PL_DDR3_DQS2_P
PL_DDR3_DQS2_N
PL_DDR3_DQS3_P
PL_DDR3_DQS4_N
PL_DDR3_D0
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ZYNQ FPGA Development Board AC7Z100 User Manual
PS_DDR_A6_502
PS_DDR_A7_502
PS_DDR_A8_502
PS_DDR_A9_502
PS_DDR_A10_502
PS_DDR_A11_502
PS_DDR_A12_502
PS_DDR_A13_502
PS_DDR_A14_502
PS_DDR_BA0_502
PS_DDR_BA1_502
PS_DDR_BA2_502
PS_DDR_CS_B_502
PS_DDR_RAS_B_502
PS_DDR_CAS_B_502
PS_DDR_WE_B_502
PS_DDR_ODT_502
PS_DDR_DRST_B_502
PS_DDR_CKP_502
PS_DDR_CKN_502
PS_DDR_CKE_502
ZYNQ Pin Name
IO_L3P_T0_DQS_33
IO_L3N_T0_DQS_33
IO_L9P_T1_DQS_33
IO_L9N_T1_DQS_33
IO_L15P_T2_DQS_33
IO_L15N_T2_DQS_33
IO_L21P_T3_DQS_33
IO_L21N_T3_DQS_33
IO_L5N_T0_33
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H26
K22
F27
J23
G26
H24
K23
H23
J24
M27
M26
M25
N22
N24
M24
N23
L23
F25
K25
J25
M22
ZYNQ Pin Number
K3
K2
J1
H1
E6
D5
A5
A4
J3