Alinx AC7Z100 User Manual page 23

supply generates +1.2V power required by GTX through the LDO chip
TPS74401, and +3.3V generates GTX auxiliary power supply +1.8V through an
LDO chip SPX3819-1-8. The VTT and VREF voltages of the DDR3 of the PS
section and the PL section are generated by U7, U10. In addition, the IO power
supply of BANK10
SPX3819M5-3-3. Users can change the IO input and output of these two
BANKs to other voltage standards by replacing the LDO chip.
The functions of each power distribution are shown in the following table:：
Power Supply
+1.0V
+1.8V
+3.3V
+1.5V
VCCIO10
VCCIO11
VREF,VTT(+0.75V)
MGTAVCC(+1.0V)
MGTAVTT(+1.2V)
MGTVCCAUX(+1.8V)
Because the power supply of the ZYNQ FPGA has the power-on
sequence requirements, in the circuit design, we have designed according to
the power requirements
+1.0V->+1.8V->(+1.5 V, +3.3V, VCCIO10,VCCIO11) circuit design to ensure
the normal operation of the chip.
The physical diagram of the power circuit on the AX7Z100 core board is
shown in Figure 9-2:
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ZYNQ FPGA Development Board AC7Z100 User Manual
and BANK11
ZYNQ PS and PL section Core Voltage
ZYNQ PS and PL partial auxiliary voltage,BANK501, BANK35, eMMC
ZYNQ Bank0,Bank500, Bank9,Bank12, Bank13
DDR3, ZYNQ Bank501, Bank33,Bank34,
ZYNQ Bank109, Bank110, Bank111, Bank112
ZYNQ Bank109, Bank110, Bank111, Bank112
ZYNQ Bank109, Bank110, Bank111, Bank112
of the
Amazon Store: https://www.amazon.com/alinx
are generated
Function
QSIP FLASH, Clock Crystal
ZYNQ Bank10
ZYNQ Bank11
PS DDR3，PL DDR3
chip. The power-on
by two-channel
sequence is