Alinx AC7Z100 User Manual page 10

Figure 3-2: The Schematic Part of DDR3 DRAM on the PL side
PS side DDR3 DRAM pin assignment:
Signal Name
PS_DDR3_DQS0_P
PS_DDR3_DQS0_N
PS_DDR3_DQS1_P
PS_DDR3_DQS1_N
PS_DDR3_DQS2_P
PS_DDR3_DQS2_N
PS_DDR3_DQS3_P
PS_DDR3_DQS4_N
PS_DDR3_D0
PS_DDR3_D1
PS_DDR3_D2
PS_DDR3_D3
PS_DDR3_D4
PS_DDR3_D5
PS_DDR3_D6
PS_DDR3_D7
PS_DDR3_D8
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ZYNQ FPGA Development Board AC7Z100 User Manual
ZYNQ Pin Name
PS_DDR_DQS_P0_502
PS_DDR_DQS_N0_502
PS_DDR_DQS_P1_502
PS_DDR_DQS_N1_502
PS_DDR_DQS_P2_502
PS_DDR_DQS_N2_502
PS_DDR_DQS_P3_502
PS_DDR_DQS_N3_502
PS_DDR_DQ0_502
PS_DDR_DQ1_502
PS_DDR_DQ2_502
PS_DDR_DQ3_502
PS_DDR_DQ4_502
PS_DDR_DQ5_502
PS_DDR_DQ6_502
PS_DDR_DQ7_502
PS_DDR_DQ8_502
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ZYNQ Pin Number
C26
B26
C29
B29
G29
F29
L28
L29
A25
E25
B27
D25
B25
E26
D26
E27
A29