Alinx AC7Z100 User Manual page 28

31 BANK112_TX0_N
33 BANK112_TX0_P
35 GND
37 BANK112_TX1_N
39 BANK112_TX1_P
41 GND
43 BANK112_TX2_N
45 BANK112_TX2_P
47 GND
49 BANK112_TX3_N
51 BANK112_TX3_P
53 GND
55 BANK112_CLK0_N
57 BANK112_CLK0_P
59 GND
61 BANK109_RX2_N
63 BANK109_RX2_P
65 GND
67 BANK109_RX3_N
69 BANK109_RX3_P
71 GND
73 BANK109_RX1_P
75 BANK109_RX1_N
77 GND
79 BANK109_TX1_P
81 BANK109_TX1_N
83 GND
85 BANK109_TX2_P
87 BANK109_TX2_N
89 GND
91 BANK109_TX3_P
93 BANK109_TX3_N
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ZYNQ FPGA Development Board AC7Z100 User Manual
T1
T2
-
R3
R4
-
P1
P2
-
N3
N4
-
N7
N8
-
AG7
AG8
-
AE7
AE8
-
AJ8
AJ7
-
AK6
AK5
-
AJ4
AJ3
-
AK2
AK1
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32 BANK112_RX0_N
34 BANK112_RX0_P
36 GND
38 BANK112_RX1_N
40 BANK112_RX1_P
42 GND
44 BANK112_RX2_N
46 BANK112_RX2_P
48 GND
50 BANK112_RX3_N
52 BANK112_RX3_P
54 GND
56 BANK112_CLK1_N
58 BANK112_CLK1_P
60 GND
62 BANK110_RX0_N
64 BANK110_RX0_P
66 GND
68 BANK110_TX0_N
70 BANK110_TX0_P
72 GND
74 BANK110_RX1_N
76 BANK110_RX1_P
78 GND
80 BANK110_TX1_N
82 BANK110_TX1_P
84 GND
86 BANK110_RX2_N
88 BANK110_RX2_P
90 GND
92 BANK110_TX2_N
94 BANK110_TX2_P
V5
V6
-
U3
U4
-
T5
T6
-
P5
P6
-
R7
R8
-
AH5
AH6
-
AH1
AH2
-
AG3
AG4
-
AF1
AF2
-
AF5
AF6
-
AE3
AE4