Quectel LTE-A Series Hardware Design page 46

The module supports 16-bit linear data format. The following figures show the relationship between 8 kHz
PCM_SYNC and 2048 kHz PCM_CLK in the primary mode.
PCM_CLK
PCM_SYNC
PCM_DOUT
PCM_DIN
The following table shows the pin definition of PCM and I2C interfaces which can be applied on audio
codec design.
Table 14: Pin Definition of PCM and I2C Interfaces
Pin Name Pin No.
PCM_DIN 66
PCM_DOUT 68
PCM_SYNC 65
PCM_CLK 67
I2C_SCL 43
I2C_SDA 42
Clock and mode can be configured by AT command, and the default configuration is master mode using
EG060V-EA_Hardware_Design
1 2
MSB
MSB
Figure 23: Primary Mode Timing
I/O Description
DI PCM data input
DO PCM data output
IO PCM data frame sync
IO PCM clock
I2C serial clock (or
OD
external codec)
I2C serial data (for
OD
external codec)
EG060V-EA Hardware Design
125 μs
255 256
LSB MSB
MSB
LSB
Comment
1.8 V power domain.
If unused, keep it open.
1.8 V power domain.
If unused, keep it open.
1.8 V power domain. In master mode, it
is an output signal. In slave mode, it is
an input signal.
If unused, keep it open.
1.8 V power domain. In master mode, it
is an output signal. In slave mode, it is
an input signal.
If unused, keep it open.
Needs to be pulled up to 1.8 V.
LTE-A Module Series
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