Wlan Control Interface - Quectel LTE-A Series Hardware Design

PCIE_RST_N 189
PCIE_WAKE_N 190
In order to enhance the module's reliability and usability in applications, please follow the criteria below in
PCIe interface circuit design:
⚫
Keep PCIe data and control signals away from sensitive circuits and signals, such as RF, audio, and
19.2 MHz clock signals.
⚫
A capacitance should be added in series on Tx/Rx traces to remove any DC bias.
⚫
Keep the maximum trace length less than 300 mm.
⚫
The length difference of the Tx or Rx differential pair of PCle traces should be less than 0.7 mm.
The differential impedance of PCIe data traces should be 100 Ω ±10 %.
⚫
⚫
PCIe data traces must not be routed under components or crossing other traces.
NOTE
"*" means under development.

3.18. WLAN Control Interface*

EG060V-EA provides a low power PCIe interface* and a control interface for WLAN design. The following
table shows the pin definition of WLAN control interface.
Table 22: Pin Definition of WLAN Control Interface
Pin Name Pin No.
WLAN_PWR_EN 5
WLAN_WAKE 160
WLAN_EN 149
COEX_RXD 146
EG060V-EA_Hardware_Design
IO PCIe reset
IO PCIe wake up
I/O Description
DO WLAN power supply enable control
Wake up the host by an external
DI
Wi-Fi module
DO WLAN function enable control
DI LTE&WLAN coexistence receive
LTE-A Module Series
EG060V-EA Hardware Design
If unused, keep it open.
In master mode, it is an output
signal.
In slave mode, it is an input signal.
If unused, keep it open.
In master mode, it is an input signal.
In slave mode, it is an output signal.
If unused, keep it open.
Comment
1.8 V power domain
1.8 V power domain
1.8 V power domain
1.8 V power domain
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