Adc Interfaces - Quectel LTE-A Series Hardware Design

short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. Please refer to
AT+QDAI command in document [1] for details.
The following figure shows a reference design of PCM interface with an external codec IC.
PCM_CLK
PCM_SYNC
PCM_DOUT
PCM_DIN
I2C_SCL
I2C_SDA
Module
1.8 V
Figure 24: Reference Design of PCM Interface with Audio Codec
NOTES
It is recommended to reserve an RC (R = 22 Ω, C = 22 pF) circuit on the PCM lines, especially for
1.
PCM_CLK.
2. EG060V-EA works as a master device pertaining to I2C interface.

3.13. ADC Interfaces

The module provides two Analog-to-Digital Converters (ADC) interfaces. AT+QADC=0 command and
AT+QADC=1 command can be used respectively to read the voltage value on ADC0 pin and ADC1 pin.
For more details about these AT+QADC commands, please refer to document [1].
In order to improve the accuracy of reading, the trace of ADC should be surrounded by ground.
EG060V-EA_Hardware_Design
EG060V-EA Hardware Design
MICBIAS
BCLK
LRCK
DAC
ADC
LOUTP
SCL
SDA
LOUTN
Codec
LTE-A Module Series
INP
INN
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