Quectel LTE-A Series Hardware Design page 44

DBG_RXD 136
The logic levels are described in the following table.
Table 13: Logic Level Parameters of Digital I/O
Item
V
IL
V
IH
V
OL
V
OH
The module provides 1.8 V UART interfaces. A level translator should be used if the application is
equipped with a 3.3 V UART interface. A level translator TXS0108EPWR provided by Texas Instruments
is recommended. Below is a reference design.
VDD_EXT
0.1 μF
VDD_EXT
MAIN_RI
MAIN_DCD
MAIN_CTS
MAIN_RTS
MAIN_DTR
MAIN_TXD
MAIN_RXD
Please visit http://www.ti.com for more information on the recommended translator.
Another approach to level translation is with a transistor translation circuit. A reference design in this
regard is shown below. For the design of circuits shown by dotted lines, both input and output circuit
designs, refer to the circuits shown by the solid lines, but please pay attention to the direction of
connection.
EG060V-EA_Hardware_Design
DI Debug UART receive
Min.
-0.3
1.2
0
1.35
VCCA
10K
OE
120K
A1
A2
Translator
A3
A4
A5
A6
A7
51K
A8
Figure 21: Reference Design of Translator Chip
EG060V-EA Hardware Design
1.8 V power domain
Max.
0.6
2.0
0.45
1.8
VCCB
0.1 μF
GND
B1
B2
B3
B4
B5
B6
B7
51K
B8
LTE-A Module Series
Unit
V
V
V
V
VDD_MCU
RI_MCU
DCD_MCU
CTS_MCU
RTS_MCU
DTR_MCU
RXD_MCU
TXD_MCU
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