Quectel RM500Q-AE Manual page 44

PCM_CLK
PCM_SYNC
PCM_DOUT
PCM_DIN
The following table shows the pin definition of PCM interface which can be applied to audio codec design.
Table 121211: Pin Definition of PCM
Pin No. Pin Name
20 PCM_CLK
22 PCM_DIN
24 PCM_DOUT
28 PCM_SYNC
The clock and mode can be configured by AT command, and the default configuration is master mode
using short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. See
document [2] for details about AT+QDAI command.
NOTE
"*" means under development.
RM500Q-AE&RM502Q-AE_Hardware_Design
125 μs
1 2
MSB
MSB
Figure 2122: Auxiliary Mode Timing
Interface*
I/O Description
IO PCM data bit clock
DI PCM data input
DO PCM data output
IO PCM data frame sync
RM500Q-AE&RM502Q-AE Hardware Design
31 32
LSB
LSB
Comment
1.8 V power domain
In master mode, it is an output signal.
In slave mode, it is an input signal.
If unused, keep it open.
1.8 V power domain
1.8 V power domain
1.8 V power domain
5G Module Series
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