Quectel RM500Q-AE Manual page 33

Host
Figure 11: Reference Circuit of RESET_N with NMOS Driving Circuit
The reset scenario is illustrated in the following figure.
Module Status
RM500Q-AE&RM502Q-AE_Hardware_Design
Reset pulse
GPIO
R4
10R
S1 TVS C1
33 pF
VCC
≥200 ms
RESET_N
Running
Figure 1213: Resetting Timing of the Module
RM500Q-AE&RM502Q-AE Hardware Design
RESET_N
Q2
NMOS
R5
200-700 ms
100k
VDD 1.5V
R1
100k
RESET_N 67
200-700 ms
≤ 700 ms
≤ 0.5 V
V
IL
Resetting Restart
5G Module Series
Module
VDD 1.5 V
R1
100k
67
Reset
Logic
Reset
Logic
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