Quectel RM500Q-AE Manual page 41

Figure 18: PCIe Power-on Timing Requirements of M.2 Specification
FUL L_CARD_ POWER_OFF
RFFE_ VIO _1V8
PICE_REFCL K
Figure 19: PCIe Power-on Timing Requirements of the Module
The following principles of PCIe interface design should be complied with, so as to meet PCIe
specification.
⚫
Keep the PCIe data and control signals away from sensitive circuits and signals, such as RF, audio,
crystal and oscillator signals.
⚫
Add a capacitor in series on Tx/Rx traces to prevent any DC bias.
⚫
Keep the maximum trace length less than 300 mm.
⚫
Keep the length matching of each differential data pair (Tx/Rx) less than 0.7 mm for PCIe routing
traces.
RM500Q-AE&RM502Q-AE_Hardware_Design
Module power-on or insertion detection
VCC
RESET_N
PICE_RST_N
RM500Q-AE&RM502Q-AE Hardware Design
t
power -on
System turn-on and booting
t
68 ms
turn-on
23 ms
TPVPGL
TPERST#_CLK ＞ 100 us
5G Module Series
V 1.19 V
IH
100 ms
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