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8V19N850 Hardware Design
This document contains general board-level hardware design information for the 8V19N850. It provides
recommendations for power rail handling, loop filter calculation, and input/output termination.
Contents
1.
Power Rails .................................................................................................................................2
1.1
Bypass Capacitors ................................................................................................................2
1.2
Power Supply Isolation ..........................................................................................................3
1.3
Loop Filter ...........................................................................................................................3
1.4
2
Order Loop Filter .............................................................................................................3
1.5
Loop Filter Calculation Examples ............................................................................................5
2.
Input/Output Interface ..................................................................................................................6
2.1
Input Termination for Reference Clock Input .............................................................................6
2.2
OX_DPLL Input (OCXO/TCXO) ..............................................................................................7
2.3
OSCI/OSCO Input (XTAL, XO, OCXO/TCXO) ...........................................................................8
2.4
Output Terminations for QCLK and QREF Drivers .....................................................................9
2.4.1.
LVPECL Type Driver Terminations .............................................................................9
2.4.2.
LVDS Type Driver Terminations ............................................................................... 14
3.
Schematic Example ................................................................................................................... 15
4.
Revision History ........................................................................................................................ 15
The simplified block diagram of 8V19N850 is shown in Figure 1. For a more detailed block diagram and in-depth
descriptions about the device, see the 8V19N850 Datasheet.
A general reference schematic example is shown in Figure 2. A larger version can also be provided in a
separate document. In this schematic, the input and output interfaces are shown for illustration purposes. For
more examples, see the Input/Output Interface section. The input topology depends on the driver type, and the
output driver termination depends on the receiver specification and structure.
X0120307 Rev.1.0
Mar 25, 2021
Figure 1. Sim plified Block Diagram
Guide
Page 1
© 2021 Renesas Electronics
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Summary of Contents for Renesas 8V19N850
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Page 1: Table Of Contents
Schematic Example ........................15 Revision History ........................15 The simplified block diagram of 8V19N850 is shown in Figure 1. For a more detailed block diagram and in-depth descriptions about the device, see the 8V19N850 Datasheet. Figure 1. Sim plified Block Diagram A general reference schematic example is shown in Figure 2. -
Page 2: Power Rails
0.1uF 10uF 100pF 0.1uF Figure 2. 8V19N850 Reference Schem atic Exam ple 1. Power Rails Bypass Capacitors To avoid signal interference, bypass capacitors are required to filter noise from switching power supplies and other devices in the system. Figure 2 shows examples of bypass capacitors on the schematic. The type of bypass capacitor will depend on the noise level and noise frequencies on the application board. -
Page 3: Power Supply Isolation
The power rails should be as noise-free as possible to support the low phase noise performance of the device PLLs. The 8V19N850 also integrates LDOs for additional noise filtering. An external ultra-low noise LDO may not be required but it is recommended for further reducing power supply noise. An LDO should have a noise level of less than 6.5uVrms from 10Hz to100kHz. - Page 4 8V19N850 Hardware Design Guide 1. Determine desired loop bandwidth fc. The fc must satisfy the following condition: >> Where, Fpd is phase detector input frequency. 2 ∗ π ∗ fc ∗ N �������� = 2. Calculate Rs Icp ∗ Kvco Where, Icp is charge pump current.
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Page 5: Loop Filter Calculation Examples
The following table shows Loop Filter Value Examples for APLL0, APLL1, APLL2, and RFPLL. The loop filter values will vary based on the application requirement. Other loop values can also be used as long as the PLLs operate at the stable region. Table 2. 8V19N850 Analog PLLs Loop Filter Values Exam ples APLL0 APLL1... -
Page 6: Input/Output Interface
Clock Input Zo = 50 LVPECL Driv er 82.5 82.5 Figure 4. Input Term ination Exam ple – 8V19N850 Reference Clock Input CLK/nCLK, Driven by a 3.3V LVPECL Driver VCC=3.3V VCC=3.3V Zo = 50 nCLK Clock Input Zo = 50 LVDS Driv er Figure 5. -
Page 7: Ox_Dpll Input (Ocxo/Tcxo)
This input can also be used for APLL0, APLL1, and APLL2 phase frequency detector input. The limitation of frequency range is provided in the 8V19N850 datasheet. When the XO_DPLL input is only used for SysAPLL or SysDPLL, a stable frequency TCXO/OCXO is required. Low frequency (e.g., 10MHz to 20MHz) is fine. Phase noise performance is not critical. -
Page 8: Osci/Osco Input (Xtal, Xo, Ocxo/Tcxo)
SysDPLL. The OCSI signal source phase noise needs to have good performance so that it provides a good close-end phase noise performance at the 8V19N850 output. The OCSI signal source can be XO, OCXO, or TCXO. -
Page 9: Output Terminations For Qclk And Qref Drivers
■ CTS17 or different frequency in the same product family. Output Terminations for QCLK and QREF Drivers The output stage of the 8V19N850 QCLK drivers can be configured to be LVPECL style driver or LVDS style driver. 2.4.1. LVPECL Type Driver Terminations... - Page 10 8V19N850 Hardware Design Guide VDDO_v Zo = 50 Zo = 50 LVPECL Driv er High Impedance Input No Built-in Termination Figure 11. LVPECL Style Term ination Table 3. V Values for Output Term ination in Figure 11 Output Supply Voltage Output Am plitude = 1.8V...
- Page 11 8V19N850 Hardware Design Guide VDDO_v VDDO_v Zo = 50 Zo = 50 LVPECL Driv er High Impedance Input No Built-in Termination Figure 12. Alternative LVPECL Style Term ination Table 4. Resistor Values for Output Term ination in Figure 12 Output Supply Voltage...
- Page 12 8V19N850 Hardware Design Guide VDDO_v Zo = 50 Zo = 50 LVPECL Driv er High Impedance Input No Built-in Termination 0.1uF(optional) Figure 13. Alternative LVPECL Style Term ination Table 5. Resistor Values for Output Term ination in Figure 13 Output Supply Voltage Am plitude = 1.8V...
- Page 13 8V19N850 Hardware Design Guide VDDO_v LVPECL Driv er Zo = 50 Zo = 50 High Impedance Input No Built-in Termination Figure 14. Alternative LVPECL Style Term ination Table 6. Resistor Values for Output Term ination in Figure 14 Output Supply Voltage...
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Page 14: Lvds Type Driver Terminations
8V19N850 Hardware Design Guide 2.4.2. LVDS Type Driver Terminations Unlike the LVPECL style driver, the LVDS style driver does not require a board level pull-down resistor. Figure 15 and Figure 16 show typical termination examples with DC coupling for the LVDS style driver. A termination example with AC coupling is shown in Figure 17. -
Page 15: Schematic Example
8V19N850 Hardware Design Guide 3. Schematic Example A reference demonstration board schematic and the board layout are available upon request: ■ 8V19N850 EVB schematic ■ 8V19N850 EVB board layout 4. Revision History Revision Date Description Mar 25, 2021 Initial release. - Page 16 Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
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