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8V19N49x Hardware Design Guide
2.2
Power Supply Isolation
Analog power rails require cleaner power to optimize the jitter performance of PLLs. Most parts in the N49x family
contain built-in LDOs. An external ultra-low noise LDO may not be required but it is recommended for reducing
power supply noise for noise-sensitive power lines such as VDD_LCF and the external VCXO. An LDO with a
noise level of less than 6uVrms from 10Hz to100kHz is recommended. This ultra-low noise LDO is mainly for the
external VCXO that does not have a built-in LDO, and this affects the performance of 100Hz to 100kHz region.
It is suggested to isolate the analog power rail from other high-noise power rails. The isolation can be
implemented through an RC low pass filter. The larger RC component values can reduce the cutoff frequency
further and clean up lower frequency noise. For the VDDO output supplies, to reduce output frequency
interference, the power rails between the output banks that operate at different output frequencies can be isolated
using separate LDOs or using 1 to 2 ohm resistors if they share the same power source. Additional smaller value
capacitors (e.g., 100pF) in parallel with the existing 0.1uF near the power pins can provide additional higher
frequency noise filtering.
3.
Loop Filter
nd
3.1
2
Order Loop Filter
This section provides design guidelines for a 2
in
Figure
6. In addition, a step-by-step calculation is provided to determine Rs, Cs, and Cp values. The required
parameters for this part are also provided. A software tool for calculating the loop filter values is also available.
1. Determine the desired loop bandwidth, fc. The fc must satisfy the following condition:
Fpd
20
fc
Where,
Fpd is phase-detector input frequency.
2. Calculate Rs.
Where,
Icp is charge pump current.
Kvco is VCO gain.
R31UH0005EU0100 Rev.1.0
Jun 3, 2021
nd
order loop filter for PLL. A typical 2
Charge Pump Driv er
Rs
Cs
nd
Figure 6. Typical 2
Order Loop Filter
nd
Cp
Loop Filter Return
order loop filter is displayed
Page 5
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